A novel high-performance and reliable multi-threshold CNFET full adder cell design

Mehrabani, Yavar Safaei; Shafiabadi, Mohammad Hossein

doi:10.1504/ijhpsa.2017.10004505

Cited by 4 publications

(5 citation statements)

References 25 publications

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“…Each unit cell of the graphene ribbon is defined by the vectors a1 and a2 as depicted in Fig.1. The tube is formed by rolling the sheet based on the chiral axis parallel to the translational vector T [2].…”

Section: Fig1 Structure Of Cntfet [3]mentioning

confidence: 99%

“…2, the angle θ formed between Ch and a1 is very important in measuring the electronic properties of the single walled carbon nano tube. It is known as the angle of chirality [2].…”

Section: Fig1 Structure Of Cntfet [3]mentioning

confidence: 99%

“…The single walled CNTs can be categorized into two types: [3] Zig Zag and armchair nanotubes having chiral values, Ch = (n,n) and Ch = (n,0), respectively [2]. In the proposed work, we have considered a planar MOSFET like CNTFET with zigzag semiconducting SWCNT to determine the voltage vs drain current characteristics upon variation of diameter.…”

Section: Fig1 Structure Of Cntfet [3]mentioning

confidence: 99%

“…These devices have enormously constructive Characteristics in submicron regime in comparison with conventional MOSFETs and yields greater performance when considered for SoC design. Due to the similarities in the operational characteristics with that of MOSFET and a low off state-current during cut-off, the CNTFET appears to be more promising successor to the conventional MOSFET technology [2]. Implementation of adders using CNTFET leverages the advantage of fast processing when employed in multiply and accumulate (MAC) units of SoCs.…”

Section: Introductionmentioning

confidence: 99%

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Cntfet Based Novel 14t Adder Cell for Low Power Computation

Ramakrishna¹,

Aswatha²

2017

IJME

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This paper focuses on the design of a 14 transistor one bit adder cell designed using CNTFET 32nm Technology to address the power and speed issues of high performance computational systems. The performance metrics of the proposed adder cell is compared by benchmarking with conventional full adder design, Transmission gate based full adder and Shannon's expression based full adders using CNTFET technology. The proposed design has lesser delay and very low power consumption. The design embraces Stanford 32nm planar CNTFET library model with a power supply of 1 volt and single walled CNT. Extensive simulation has been carried out on the adder cells considered and the parameters such as power, delay and PDP are investigated. The effect of temperature variation on the power consumption of proposed 14T adder cell is also observed to examine the robustness. The simulation results demonstrate that the proposed adder delivers stable output drivability with substantial diminution in the leakage power.

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Section: Fig1 Structure Of Cntfet [3]mentioning

confidence: 99%

“…2, the angle θ formed between Ch and a1 is very important in measuring the electronic properties of the single walled carbon nano tube. It is known as the angle of chirality [2].…”

Section: Fig1 Structure Of Cntfet [3]mentioning

confidence: 99%

Section: Fig1 Structure Of Cntfet [3]mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Cntfet Based Novel 14t Adder Cell for Low Power Computation

Ramakrishna¹,

Aswatha²

2017

IJME

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“…Carbon nanotubes (CNTs) are rolling sheets of graphite and they are divided into two categories called single-walled carbon nanotubes (SWCNTs) and multi-walled carbon nanotubes (MWCNTs) (McEuen et al , 2002). The SWCNT consists of one cylinder while the MWCNT consists of more than one cylinder nested together with interlayer spacing of 3.4 angstrom (Safaei Mehrabani and Shafiabadi, 2017). The pair ( n 1 , n 2 ) called chirality vector specifies the arrangement angle of carbons along the CNT (Lin et al , 2009).…”

Section: Introductionmentioning

confidence: 99%

A low-PDAP and high-PSNR approximate 4:2 compressor cell in CNFET technology

Mehrabani

Bagherizadeh

Shafiabadi

et al. 2019

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Purpose This paper aims to present an inexact 4:2 compressor cell using carbon nanotube filed effect transistors (CNFETs). Design/methodology/approach To design this cell, the capacitive threshold logic (CTL) has been used. Findings To evaluate the proposed cell, comprehensive simulations are carried out at two levels of the circuit and image processing. At the circuit level, the HSPICE software has been used and the power consumption, delay, and power-delay product are calculated. Also, the power-delaytransistor count product (PDAP) is used to make a compromise between all metrics. On the other hand, the Monte Carlo analysis has been used to scrutinize the robustness of the proposed cell against the variations in the manufacturing process. The results of simulations at this level of abstraction indicate the superiority of the proposed cell to other circuits. At the application level, the MATLAB software is also used to evaluate the peak signal-to-noise ratio (PSNR) figure of merit. At this level, the two primary images are multiplied by a multiplier circuit consisting of 4:2 compressors. The results of this simulation also show the superiority of the proposed cell to others. Originality/value This cell significantly reduces the number of transistors and only consists of NOT gates.

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