2019 10th International Conference on Computing, Communication and Networking Technologies (ICCCNT) 2019
DOI: 10.1109/icccnt45670.2019.8944888
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A Novel Hybrid Full Adder Based on Gate Diffusion Input Technique, Transmission Gate and Static CMOS Logic

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Cited by 30 publications
(17 citation statements)
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“…By this scheme, the circuit could ensure better speed. HBD 3 [46], GDI 2 [65], and GDI 3 [66] are close contesters of HBD 7 [50] in speed. Speed of CPL [25] and CCMOS [30] FAs are quite satisfactory in spite of being some of the oldest FA topologies.…”
Section: Performance Of Fas As Single Cellsmentioning
confidence: 80%
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“…By this scheme, the circuit could ensure better speed. HBD 3 [46], GDI 2 [65], and GDI 3 [66] are close contesters of HBD 7 [50] in speed. Speed of CPL [25] and CCMOS [30] FAs are quite satisfactory in spite of being some of the oldest FA topologies.…”
Section: Performance Of Fas As Single Cellsmentioning
confidence: 80%
“…In spite of excellent performance in speed, CPL [25] has very high PDP due to its high average power. 16-T [36], HBD 1 [45], HBD 2 [45], HBD 3 [46], HBD 4 [47], GDI 1 [64], GDI 2 [65], GDI 3 [66], GDI 4 [66] and GDI 5 [66] have considerably low PDP compared to other FAs.…”
Section: Performance Of Fas As Single Cellsmentioning
confidence: 95%
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“…Full Adder cell is the basic cell for addition of two binary bits [18][19]. However, in modern processors, implementation of wide adders is required.…”
Section: Introductionmentioning
confidence: 99%