A Novel Implementation of Binary Coded Decimal Based Logic Divider Uding Vedic Direct Flag Method and its Application in Key Generation in RSA Gryptographic Algorithm.

Abstract

Reversible logic does not dissipate energy and information loss never occurs. So, this futuristic technology is forced towards many applications involving less energy dissipation. This work targets the design of new Vedic divider circuit and its implementation using reversible gates. Direct Flag Vedic Division Method (DFVDM) is a new methodology and it is addressed in this proposed work using reversible logic. We have utilized basic reversible gates in the block level construction and showed that the proposed Reversible Direct Flag Vedic Division Method (RDFVDM) implementation is having quantum parameter as well as ASIC parameter efficiency. This divider circuit inherits many advantages such as fewer garbage outputs, minimum quantum cost. Simulation investigations have been done by CADENCE EDA Tool. The proposed Vedic divider is also compared using the reversible structural metrics like garbage outputs, constant inputs, quantum cost with existing works and results showcases that RDFVDM excels than the equivalent designs.