A Novel Low-Complexity and Energy-Efficient Ternary Full Adder in Nanoelectronics

Hosseini, Seied Ali; Etezadi, Sajjad

doi:10.1007/s00034-020-01519-2

Cited by 16 publications

(16 citation statements)

References 36 publications

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“…The other two papers have been published by IEEE ELECTRON DEVICE LETT [33] and IEEE OJ-NANO [34]. Furthermore, CSSP (Springer) [35][36][37][38][39][40][41][42] and MICROELECTR J (Elsevier) [43][44][45][46][47][48][49][50] with eight papers each, and INT J ELECTRON (Taylor & Francis) [51][52][53][54][55] and IET CIRC DEVICE SYST (IET/IEE) [56][57][58][59][60] with five papers each are the journals with the highest number of publications relevant to the subject of THAs and TFAs in other publishers. IEEE ISMVL, with 11 papers [61][62][63][64][65][66][67][68][69][70][71], is the one that stands out among conferences.…”

Section: Research Methods and Bibliographic Informationmentioning

confidence: 99%

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Comprehensive survey of ternary full adders: Statistics, corrections, and assessments

Nemati

Kashani

Mirzaee

2023

IET Circuits, Devices & Syst

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The history of ternary adders goes back to more than 6 decades ago. Since then, a multitude of ternary full adders (TFAs) have been presented in the literature. This article conducts a review of TFAs so that one can be familiar with the utilised design methodologies and their prevalence. Moreover, despite numerous TFAs, almost none of them are in their simplest form. A large number of transistors could have been eliminated by considering a partial TFA instead of a complete one. According to our investigation, only 28.6% of the previous designs are partial TFAs. Also, they could have been simplified even further by assuming a partial TFA with an output carry voltage of 0 V or V DD . This way, in a single-V DD design, voltage division inside the Carry generator part would have been eliminated and less power dissipated. As far as we have searched, there are only three partial TFAs with this favourable condition in the literature. Additionally, most of the simulation setups in the previous articles are not realistic enough. Therefore, the simulation results reported in these papers are neither comparable nor entirely valid. Therefore, the authors got motivated to conduct a survey, elaborate on this issue, and enhance some of the previous designs. Among 84 papers, 10 different TFAs (from 11 papers) are selected, simplified, and simulated in this article. Simulation results by HSPICE and 32 nm carbon nanotube FET technology reveal that the simplified partial TFAs outperform their original versions in terms of delay, power, and transistor count. K E Y W O R D Sadders, carbon nanotube field effect transistors, digital arithmetic, multivalued logic, multivalued logic circuits, ternary logicThis is an open access article under the terms of the Creative Commons Attribution-NonCommercial License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited and is not used for commercial purposes.

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Section: Research Methods and Bibliographic Informationmentioning

confidence: 99%

“…After eliminating the above varieties, 25 papers remain [13, 17, 18, 21, 35–37, 44, 58, 60, 67, 69, 71, 87, 95, 101–108, 131, 132]. However, many of them follow similar structures.…”

Section: Literature Review and Backgroundmentioning

confidence: 99%

Comprehensive survey of ternary full adders: Statistics, corrections, and assessments

Nemati

Kashani

Mirzaee

2023

IET Circuits, Devices & Syst

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“…A lot of ternary full adders have been published in the last decade [3][4][5][6][7][8][9][10][11]. They use different techniques quoted in ternary half adders in [12], the technique using A¹ and A² operators and MUXes may be considered as the most efficient one.…”

Section: Related Workmentioning

confidence: 99%

“…For all simulations, the input waveforms shown in Figs. 15, 16 and 17 are used. It has been verified that the delays for 0-2 or 2-0 ternary transitions are always less than for ternary transitions 0-1, 1-2, 2-1 or 1-0.…”

Section: Power Dissipation and Power-delay Product (Pdp)mentioning

confidence: 99%

Post algebras and ternary adders

Etiemble

2023

Journal of Electrical Systems and Inf Technol

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Except for qubits for which the different possible values are unordered, the different values of m-valued circuits either with voltage levels, current levels or charge levels are totally ordered. Either at the Math level (Post algebras) or at the circuit level, it means that each multiple valued level must be decomposed into binary levels, processed with binary computation and finally converted into a multiple valued level. Using ternary adders as example, we show that the ternary-to-binary decoding and binary encoding should be applied to the whole adder or to restricted parts of the adder. The second approach using multiplexers leads to the most efficient ternary adders. However, a comparison with binary adders shows that the ternary-to-binary and binary-to-ternary conversions is the reason for which the binary adders are more efficient.

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“…The truth table of the ternary full adder is as shown in Table 1. 19 C in is the carry input signal which only has 0 and 1 two states. A and B are the ternary input signals.…”

Section: Mathematical Analysis Of Ternary Memristor Full Addermentioning

confidence: 99%

A ternary memristor full adder based on literal operation and module operation

Lin

Han

Luo

et al. 2022

Circuit Theory & Apps

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A ternary memristor full adder is designed based on the literal operation and module‐3 plus operation. Literal operation and module‐3 plus operation are the important operations in the tri‐valued algebra system. Multiple‐valued logic can increase the amount of information carried by the signals and reduce the number of devices and connections. The combination of multiple‐valued logic and memristor is an exploration of new devices and new structures. The novel ternary memristor full adder owns the advantage of simpler structure without decoding units to convert ternary signals to binary at the terminals, and all the signals operated by the circuit are ternary. Compared with the traditional ternary full adder, the number of devices and the power consumption are greatly reduced. Simulation results of different memristor models verified the correctness and applicability of the circuit design. It provides a new idea for the design method of memristor circuits, especially multiple‐valued memristors.

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A Novel Low-Complexity and Energy-Efficient Ternary Full Adder in Nanoelectronics

Cited by 16 publications

References 36 publications

Comprehensive survey of ternary full adders: Statistics, corrections, and assessments

Comprehensive survey of ternary full adders: Statistics, corrections, and assessments

Post algebras and ternary adders

A ternary memristor full adder based on literal operation and module operation

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