A novel low power double edge triggered flip-flop based on clock gated pulse suppression technique

Kavali, Krishna; Rajendar, S.; Bhargava, P. Vamshi

doi:10.1109/eesco.2015.7253849

2015 International Conference on Electrical, Electronics, Signals, Communication and Optimization (EESCO) 2015

DOI: 10.1109/eesco.2015.7253849

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A novel low power double edge triggered flip-flop based on clock gated pulse suppression technique

Krishna Kavali¹,

S. Rajendar²,

P. Vamshi Bhargava³

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A novel low power double edge triggered flip-flop based on clock gated pulse suppression technique

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References 18 publications

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