A Novel Method to Analyze the Deep Trench Capacitors in DRAM

Abstract

A novel method has been developed to reveal the entire three dimensional (3D) deep trench (DT) capacitors for inspection in DRAM, especially NO capacitor dielectrics, ASG residues at corners, morphology etc., for process evaluation and failure analysis. It offers an alternative to conventional cross-section polishing, top down polishing or FIB milling methods. A DRAM chip was ground and polished down to a certain level from the chip backside. An etching solution was then applied to enhance the DTs appearance. 3D DTs can be inspected in scanning electron microscopy (SEM). The entire DTs or specific DT also can be lifted out for detailed investigation in transmission electron microscopy (TEM). The innovation of this technique is to provide a quick 3D observation in SEM, and much more flexibility to an entire DT inspection in TEM, which were not presented before.