A novel methodology for the design of application-specific instruction-set processors (ASIPs) using a machine description language

Hoffmann, Andreas; Kogel, Tim; Nohl, Achim; Braun, Gunnar; Schliebusch, Oliver; Wahlen, Oliver; Wieferink, Andreas; Meyr, H.

doi:10.1109/43.959863

Cited by 126 publications

(44 citation statements)

References 22 publications

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“…A unified design method for ASIP design which provides a common basis for all design phases is proposed in [7], [8]. This method is Language for Instruction-set Architectures (LISA).…”

Section: Copyright C 2014 the Institute Of Electronics Information Amentioning

confidence: 99%

Retargeting Derivative-ASIP with Assembly Converter Tool

Bejo

Isshiki

et al. 2014

IEICE Trans. Inf. & Syst.

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SUMMARYThis paper firstly presents a processor design with Derivative ASIP approach. The architecture of processor is designed by making use of a well-known embedded processor's instruction-set as a base architecture. To improve its performance, the architecture is enhanced with more hardware resources such as registers, interfaces and instruction extensions which might achieve target specifications. Secondly, a new approach for retargeting compiler by means of assembly converter tool is proposed. Our retargeting approach is practical because it is performed by the assembly converter tool with a simple configuration file and independent from a base compiler. With our proposed approach, both architecture flexibility and a good quality of assembly code can be obtained at once. Compared to other compilers, experiments show that our approach capable of generating code as high efficiency as its base compiler and the developed ASIP results in better performance than its base processor.

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“…A unified design method for ASIP design which provides a common basis for all design phases is proposed in [7], [8]. This method is Language for Instruction-set Architectures (LISA).…”

Section: Copyright C 2014 the Institute Of Electronics Information Amentioning

confidence: 99%

Retargeting Derivative-ASIP with Assembly Converter Tool

Bejo

Isshiki

et al. 2014

IEICE Trans. Inf. & Syst.

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“…An explorer with performance estimator is shown in Figure 2. Examples of such approaches are [4][5][6][7][8][9][10][11][12][13][14][15].…”

Section: Fig 1: Asip Design Methodologymentioning

confidence: 99%

ADA: Applications Define ASIP

Jain¹

2014

IJCA

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Interest in Application Specific Instruction set Processors or ASIPs has increased significantly. Sincere efforts have been put in improving ASIP design methodologies in industry as well as in academia. By the close observation and analysis of these approaches, it was found that though the existing approaches are focusing on making the process automatic and providing better GUI to help the designers, core technique used in deciding the suitable architecture (processor and memory) is based on design space exploration. This exploration is done with the help of estimators. Such estimators are either simulator based or scheduler based. This study identifies that both types of techniques are very far from the ideal dream technique in which applications should have defined the suitable architecture configuration and these techniques are becoming unsuitable in current scenario. Each problem has a solution hidden in it. This scenario motivated us to propose a novel and revolutionary ASIP design technique making the dream true. The Proposed technique does not focuses on design space exploration, it focuses on directly defining processors for given applications rather than searching for suitable configuration in a jungle of configurations can be suggested by the architecture design space. General TermsComputer Architecture, Processor Design, Processor Design Technology.

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“…Greedy cycles from the state diagram we can determine optimal latency cycles which result in the MAL. There are infinitely many latencies cycles, one can from state diagram, suppose that (1,12), (1,4,6,8,10,12), (4,6), (4,6,8)…… are legitimate cycles traced from the state diagram. As simple cycles are latency cycles in which each state appear only ones.…”

Section: B Application Specific Latency Predictionmentioning

confidence: 99%

An Efficient Application Specific Memory Storage and ASIP Behavior Optimization in Embedded System

Khatwal¹,

Jain²

2016

ijacsa

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Abstract-Low power embedded system requires effective memory design system which improves the system performance with the help of memory implementation techniques. Application specific data allocation design pattern implements the memory storage area and internal cell design techniques implements data transition speeds. Embedded cache design is implemented with simulator and scheduling approaches which can reduce the cache miss behavior and improve the cache hit quantities. Cache hit optimization, delay reduction and latency prediction techniques are effective for ASIP design. The design functionality is simply specifying the tradeoff among various design metrics like performance, power, size, cost and flexibility. ASIP behavior and memory storage area optimized for low power embedded system and implements cycle time with effective scheduling techniques which implements the system performance with low power consumption.

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A novel methodology for the design of application-specific instruction-set processors (ASIPs) using a machine description language

Cited by 126 publications

References 22 publications

Retargeting Derivative-ASIP with Assembly Converter Tool

Retargeting Derivative-ASIP with Assembly Converter Tool

ADA: Applications Define ASIP

An Efficient Application Specific Memory Storage and ASIP Behavior Optimization in Embedded System

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