A Novel Multiplexer-Based Quaternary Full Adder in Nanoelectronics

Roosta, Esmail; Hosseini, Seied Ali

doi:10.1007/s00034-019-01039-8

Cited by 28 publications

(35 citation statements)

References 15 publications

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“…Quaternary logic consists of four voltage levels, as shown in Table 2. Logical functions were also introduced based on quaternary logic such as QNAND, QNOR, QNOT, and other special functions [12,14].…”

Section: Basic Principlementioning

confidence: 99%

“…For example, in the A 1 operator, when A switches on its corresponding levels (0, 1, 2, and 3), the voltage levels ( A ) of transistors T 4 , T 5 , T 6 , and T 7 are switched on, respectively. This is also the case for the A 2 and A 3 operators, which produce different output levels proportional to the input A [14]. Three types of 4 × 1, 8 × 4, and 12 × 4 MUX structures were also used in the multiplier and adder block circuit designs, and their structures are shown in Figure 4.…”

Section: Proposed Circuitsmentioning

confidence: 99%

“…In Figure 4B, the MUX 8 × 4 structures are shown, where if C = 0, transistors T 1 , T 3 , T 5 , and T 7 switch on, and if C = 1, transistors T 2 , T 4 , T 6 , and T 8 switch on and the input operator transfers to that of the output. In total, 93 CNTFET transistors were used in the full adder, and the space required decreased by 52% compared to that of [12], 32% compared to that of the first design of [14] and 41% compared to that of the second design of [14], 43% compared to that of [13], and 40% compared to that of [7].…”

Section: Proposed Circuitsmentioning

confidence: 99%

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Low energy and area efficient quaternary multiplier with carbon nanotube field effect transistors

2021

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In this study, new multiplier and adder method designs with multiplexers are proposed. The designs are based on quaternary logic and a carbon nanotube field‐effect transistor (CNTFET). The design utilizes 4 × 4 multiplier blocks. Applying specific rotational functions and unary operators to the quaternary logic reduced the power delay produced (PDP) circuit by 54% and 17.5% in the CNTFETs used in the adder block and by 98.4% and 43.62% in the transistors in the multiplier block, respectively. The proposed 4 × 4 multiplier also reduced the occupied area by 66.05% and increased the speed circuit by 55.59%. The proposed designs are simulated using HSPICE software and 32 nm technology in the Stanford Compact SPICE model for CNTFETs. The simulated results display a significant improvement in the fabrication, average power consumption, speed, and PDP compared to the current best‐performing techniques in the literature. The proposed operators and circuits are evaluated under various operating conditions, and the results demonstrate the stability of the proposed circuits.

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Section: Basic Principlementioning

confidence: 99%

Section: Proposed Circuitsmentioning

confidence: 99%

Section: Proposed Circuitsmentioning

confidence: 99%

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Low energy and area efficient quaternary multiplier with carbon nanotube field effect transistors

2021

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“…Otherwise, the tube is a semiconductor. The diameter of the CNT can be calculated by the following equation:

D_{CNT} = \frac{a_{0} \sqrt{3}}{π} \sqrt{n^{2} + m^{2} + n m},

where a 0 = 0.142 nm is the inter‐atomic distance between each carbon atom and its neighbour atom [25, 26]. The threshold voltage to turn ON the transistor is determined by the following equation:

V_{th} \approx \frac{E_{g}}{2 e} = \frac{\sqrt{3}}{3} \frac{a V_{π}}{e D_{CNT}},

where a = 2.49 Å is the carbon to carbon atom distance and V π = 3.033 eV is the carbon π–π bond energy in the tight bonding model, e is the unit electron charge, and D CNT is the CNT diameter [25, 26].…”

Section: Terminologymentioning

confidence: 99%

“…Many studies have been recently focused on the design of the multi‐valued logic in nanoelectronics using carbon nanotube field effect transistor (CNFET) such as multi‐digit ternary‐to‐binary converters [14–16], ternary full adder [17, 18], Multi‐valued Logic Comparator [19], ternary gates [20–23], Quaternary Full Adder [24, 25], ternary multipliers [26], ternary multi‐digit adders [27], ternary counter [28] and ternary memory cell [21, 29–32]. The basic architecture of static random access memory (SRAM) is organised as one or more rectangular arrays of memory cells with control circuitry.…”

Section: Introductionmentioning

confidence: 99%