A novel power-efficient IC test scheme

Abstract

A novel power-efficient IC test scheme is proposed, containing parallel test application (PTA) architecture and its procedure. PTA parallelizes the stimuli assignments and the vectors can be observed immediately once applied, which assures the shift safety timely and hence only logic test is required. The procedure contains two phases for each pattern. In shift phase, each clock chain is activated in turn and the vectors are assigned in parallel. In capture phase, all chains are captured simultaneously. Experimental results demonstrate that, compared with the traditional serial scan scheme, the proposal reduces average power by 88.48% and peak power by 53.36%.

A novel X-filling method for capture power reduction

“…The effect of IR drops is particularly problematic at near-threshold voltage condition which decreases the supply voltage to about the threshold voltage for the sake of energy efficiency. Test operations consume more power than normal operations because test patterns make large transitions in circuits under testing [1,2,3]. Timing failures that don't occur in normal operations can be generated by these test operations and these make the overkill problem [4,5].…”