A novel pseudo-floating-gate flash EEPROM device (/spl Psi/-cell)

Abstract

The purpose of this paper is to present a novel Pseudo-Floating-Gate Flash EEPROM cell which has certain advantages over the classical structure and, therefore, it seems adequate for multi-MBit memory arrays as well as for CMOS embedded memory applications. The proposed cell is based on the series resistance modification concept and exhibits the following characteristics: 1) simplicity; 2) dimensions as small as a MOSFET; 3) the ability to follow the shrink rate of CMOS devices, 4) the ability to be easily embedded in CMOS, 5) lowpower compatibility, and 6) insensitivity to depletion phenomena. All these features make this device very attractive for future NVM applications.

A Stress-Relaxed Negative Voltage-Level Converter

“…For that reason, level-conversion circuits, which convert a voltage-level signal into another voltage-level signal, are required for the proper interconnection between blocks with different operating voltages. Since negative voltages are exploited in many circuit operations (Flash memory erase operation [3], [13], DRAM refresh time enhancement [4], [5], low standby power consumption mode activation [7]- [9], ESD protection [14], and circuit calibration [15], [16]), converters that can treat negative voltages are of great importance.…”