A nullor approach to computer-aided analogue circuit diagnosis

Abstract

In this article, a nullor approach to analogue circuit diagnosis at subcircuit and at component levels is developed. The test voltages of the accessible nodes and the current through the voltage supply are selected as test quantities. A nullor diagnosis model of the circuit under test is constructed. The automated fault localization and identification of single and multiple faults is reduced to simulation of a nullor diagnosis model. The approach allows us to automatically carry out fault identification of soft (parametric) faults using standard circuit simulators. Based on the simulation of the diagnosis model of the faulty circuit, fault coverage investigation and optimal test node selection can be performed in order to increase the testability of the circuit. An example illustrating the proposed approach is presented.