A parallel elliptic curve crypto-processor architecture with reduced clock cycle for FPGA platforms

Kalaiarasi, M.; Venkatasubramani, V. R.; Thyagarajan, V. Vinoth; Rajaram, S.

doi:10.1007/s11227-022-04442-2

Cited by 4 publications

(2 citation statements)

References 36 publications

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“…Like designs, described in [38], [40], the clock cycles of our accelerator can be minimized by using multiple adders, multiplier, and square units, but with area and power overheads. Another technique that can be utilized for minimizing clock cycles of our accelerator is a quad-block version of the Itoh-Tsujii inversion algorithm, as implemented in [52], [53]. However, these optimization methods will increase hardware resource usage and power consumption.…”

Section: A Resultsmentioning

confidence: 99%

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DCryp-Unit: Crypto Hardware Accelerator Unit Design for Elliptic Curve Point Multiplication

Alharbi,

Hazzazi,

Jamal

et al. 2024

IEEE Access

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We propose a hardware-optimized design that implements a Montgomery Elliptic-curve point multiplication Algorithm over GF (2 233 ) using Lopez-Dahab projective coordinates. Moreover, we propose a digit-parallel modular multiplier, which reduces clock cycles and improves throughput. Also, we provided how to use our proposed digit-parallel multiplier for post-quantum cryptography algorithms. In addition, we use the proposed digit-parallel multiplier with the square circuit to implement the Itoh-Tsujii inversion algorithm for modular inversion computation; this permits hardware resource minimization. An efficient finite-state machine controller is implemented for control functionalities. A figure of merit in throughput/area is defined for reasonable comparison to state-of-the-art. We provide implementation results after post-place-and-route on field-programmable gate array devices. On the Virtex-7 device, our design utilizes 3386 slices and requires 7218 clock cycles; it achieves a maximum frequency of 365 MHz and computes one point multiplication in 19.77µs. The total power consumption of our design is 2027 mW. The calculated values for throughput and figure of merit are 50.58Kbps and 14.93, respectively. Consequently, the implementation results and comparisons reveal our design's suitability for applications requiring area and throughput-optimized cryptographic implementations.

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Section: A Resultsmentioning

confidence: 99%

“…The prior, implemented in [6], computes one square per clock cycle. The latter, as seen in [52], [53], performs two repeated squares in one clock cycle. In contrast, the square version reduces area with throughput overhead, while the quad version boosts throughput at the expense of area.…”

Section: ) Inversion Using Square Itoh-tsujii Algorithmmentioning

confidence: 99%