A Parallel Simulated Annealing Approach for the Mapping of Large Process Networks

Galea, François; Sirdey, Renaud

doi:10.1109/ipdpsw.2012.221

Cited by 12 publications

(6 citation statements)

References 7 publications

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“…In our future analysis, we plan to consider heterogeneous parallel applications that generate multiple hot spots on the chip. For this, we plan to use high utility applications, such as the distributed version of the simulated annealing metaheuristic algorithm [31] that recursively leads to multiple hot spots on the chip while exploring the space of solutions.…”

Section: Discussionmentioning

confidence: 99%

Introducing a Data Sliding Mechanism for Cooperative Caching in Manycore Architectures

Dahmani

Cudennec

Gogniat

2013

2013 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum

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In future micro-architectures, the increase of the number of cores and wire network complexity is leading to several performance degradation. These platforms are intended to process large amount of data. One of the biggest challenges for systems scalability is actually the memory wall: the memory latency is hardly increasing compared to technology expectations. Recent works explore potential software and hardware solutions mainly based on different caching schemes for addressing off-chip access issues.In this paper, we propose a new cooperative caching method improving the cache miss rate for manycore micro-architectures. The work is motivated by some limitations of recent adaptive cooperative caching proposals. Elastic Cooperative caching (ECC), is a dynamic memory partitioning mechanism that allows sharing cache across cooperative nodes according to the application behavior. However, it is mainly limited with cache eviction rate in case of highly stressed neighborhood. Another system, the adaptive Set-Granular Cooperative Caching (ASCC), is based on finer set-based mechanisms for a better adaptability. However, heavy localized cache loads are not efficiently managed. In such a context, we propose a cooperative caching strategy that consists in sliding data through closer neighbors. When a cache receives a storing request of a neighbor's private block, it spills the least recently used private data to a close neighbor. Thus, solicited saturated nodes slide local blocks to their respective neighbors to always provide free cache space. We also propose a new Prioritybased Data Replacement policy to decide efficiently which blocks should be spilled, and a new mechanism to choose host destination called Best Neighbor selector.The first analytic performance evaluation shows that the proposed cache management policies reduce by half the average global communication rate. As frequent accesses are focused in the neighboring zones, it efficiently improves on-Chip traffic.Finally, our evaluation shows that cache miss rate is enhanced: each tile keeps the most frequently accessed data 1-Hop close to it, instead of ejecting them Off-Chip. Proposed techniques notably reduce the cache miss rate in case of high solicitation of the cooperative zone, as it is shown in the performed experiments.

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Section: Discussionmentioning

confidence: 99%

Introducing a Data Sliding Mechanism for Cooperative Caching in Manycore Architectures

Dahmani

Cudennec

Gogniat

2013

2013 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum

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“…The CPLEX solver allows to directly encode the mathematical model described in Section 3 except for the core dynamic power (6). In the computational experiments we test the usefulness of introduced constraints and linearizations.…”

Section: Methodsmentioning

confidence: 99%

“…There are few works which treat the joined problem of task mapping and communication routing, but different from ours on certain points. Several task mapping and communication routing methods for dataflow applications on clustered many-cores are presented in [6]. Task mapping and communication routing are performed separately.…”

Section: Related Workmentioning

confidence: 99%

“…The dynamic power consumption for core c ∈ C is given by nonlinear relation (6). We note that when the available computational power Qc is zero (e.g.…”

Section: Mapping Constraintsmentioning

confidence: 99%

“…Only a single constraint from the mapping group of constraints is not linear: core dynamic power (6). We replace Gc and Qc with the right-hand sides of (2) and respectively (3) in the core dynamic power constraint.…”

Section: Constraint Linearizationmentioning

confidence: 99%

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Task mapping and communication routing model for minimizing power consumption in multi-cores

Carpov

2015

Proceedings of the 8th International Workshop on Network on Chip Architectures

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In this paper we introduce a novel MILP formulation for the problem of mapping tasks and routing communications on multi-core systems with power minimization objective. The cores have several power consumption modes. Dynamic and static power consumptions are modeled independently and the dynamic power consumption depends on core load rate. Three types of communication routing are examined: single-path, multi-path and fractional multi-path. Initially a mathematical model is introduced and afterwards a linearized mixed-integer program formulation is proposed. We conclude the paper by presenting computational results on task graph instances obtained from StreamIt applications.

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Introduction to Optimization Under Uncertainty Techniques for High-Performance Multicore Embedded Systems Compilation

Stan

Sirdey

2015

Computational Intelligence in Digital and Network Designs and Applications

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A Parallel Simulated Annealing Approach for the Mapping of Large Process Networks

Cited by 12 publications

References 7 publications

Introducing a Data Sliding Mechanism for Cooperative Caching in Manycore Architectures

Introducing a Data Sliding Mechanism for Cooperative Caching in Manycore Architectures

Task mapping and communication routing model for minimizing power consumption in multi-cores

Introduction to Optimization Under Uncertainty Techniques for High-Performance Multicore Embedded Systems Compilation

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