A Particle Swarm Optimization Approach for Low Power Very Large Scale Integration Routing

Abstract

This study deals with the particle swarm optimization approach for optimal power dissipation in VLSI interconnect driven routing technique. Interconnect power dissipation is a major challenging research problem in Deep Submicron (DSM) regime that affects the overall circuit performance. The Buffer Insertion Buffer Sizing and Wire Sizing (BISWS) is considered for minimizing the power dissipation in VLSI circuits using interconnect wires. The shortest path constraints, buffer insert constraints and wire size constraints are used to analysis the power consumption considered for analysis. The closed form expressions for optimal power allocation is also derived. These expressions can be used to estimate the power dissipation efficiently in the physical design stages of the VLSI. It is observed that the power dissipation is optimal using the shortest path between source to sink. A novel optimization algorithm is introduced to model delay and bandwidth analytically derived and analyzed. The proposed optimization algorithm is analyzed and compared for 65, 45 and 32 nm CMOS technologies.