A Pipelined, High-Precision FFT Architecture

Abstract

Publc reporting burden for this collection of inforiat~on is estimated to average 1 hour ner response. including the time for reviewing instructions, searching existing data sources, ga~thering and mantaining the data needed, and cOml:eting and revl~ing the collection of information. Approved for public release; distribution unlimited. ABSTRACT (Maximum 200 words)This paper presents a highly-integrated, high-precision FFT architecture. A 1.2 jm CMOS implementation of this architecture has yielded a 32-bit, 64K-point FFT that operates at a continuous 4-million-samples-per-second data rate. All FFT support functions, including coefficient generation and memory interfacing, are included on-chip.