A Power-Efficient Pipelined ADC with an Inherent Linear 1-Bit Flip-Around DAC

Abstract

An unity-gain 1-bit flip-around digital-to-analog converter (FADAC), without any capacitor matching issue, is proposed as the front-end input stage in a pipelined analog-to-digital converter (ADC), allowing an input signal voltage swing up to be doubled. This large input swing, coupled with the inherent large feedback factor (ideally β = 1) of the proposed FADAC, enables a power-efficient low-voltage high-resolution pipelined ADC design. The 1-bit FADAC is exploited in a SHA-less and opamp-sharing pipelined ADC, exhibiting 12-bit resolution with an input swing of 1.8 Vpp under a 1.1 V power supply. Fabricated in a 0.13-μm CMOS process, the prototype ADC achieves a measured signal-to-noise plus distortion ratio (SNDR) of 66.4 dB and a spurious-free dynamic range (SFDR) of 76.7 dB at 20 MS/s sampling rate. The ADC dissipates 5.2 mW of power and occupies an active area of 0.44 mm2. The measured differential nonlinearity (DNL) is +0.72/−0.52 least significant bit (LSB) and integral nonlinearity (INL) is +0.84/−0.75 LSB at a 3-MHz sinusoidal input.

A 2.5-GS/s Four-Way-Interleaved Ringamp-Based Pipelined-SAR ADC with Digital Background Calibration in 28-nm CMOS

“…With the evolution of the CMOS process, the design of traditional OTA, applied in amplifier-needed ADCs, is facing more and more challenges, such as the decrease of SNR due to the decrease of supply voltage and the decrease of intrinsic gain leading to nonnegligible gain errors. Additionally, linearity is an important metric to consider during design [27,28]. A ringamp has been an attractive substitution for OTA, used as a residue amplifier (RA) in pipelined or pipelined-SAR ADCs, since the primary building block of a ringamp is its inverter [29].…”