A Power Optimized Divide by N Prescaler Design on 50nm CMOS Process

Abstract

Abstract:In this paper divide by N prescaler counter is discuss. Instead of using conventional counter design technologies, a decision logic circuit is needed to generate predictable counting states. This circuit can be design by using transmission gate logic as a basic design cell. An initial module generates predictable counting states for higher significant bit modules through the state look-ahead path. In order to attain high operating frequency a high speed parallel counter is presented. In our work the counter operating frequency is varied by using a parallel counter architecture of transmission gate base flip-flops. The operation speed is improved by reduction of the critical path delay and the low power consumption can be achieved due to less number of interconnects. Simulation results in a standard 50nm CMOS process.