A practical tool box for system level communication synthesis

Hommais, Denis; Pétrot, Frédéric; Augé, Ivan

doi:10.1145/371636.371674

Cited by 12 publications

(4 citation statements)

References 8 publications

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“…This lake of RTL blocks flexibility is especially true for the communication unit (COMU) which sequence orders and/or timing requirements are fixed. These components are hence integrated in the final SoC architecture by using specific interfaces [13] or wrappers [19], that adapt the system communication features to the component requirements, i.e. the SoC integrator has to manage both IP execution requirements and integration constraints.…”

Section: Introductionmentioning

confidence: 99%

Constrained algorithmic IP design for system-on-chip

Coussy¹,

Casseau²,

Bomel³

et al. 2007

Integration

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Section: Introductionmentioning

confidence: 99%

Constrained algorithmic IP design for system-on-chip

Coussy¹,

Casseau²,

Bomel³

et al. 2007

Integration

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“…row-column), Input/Output parallelism adaptation. Based on communication templates, [9] presents a generic interface unit architecture for communication synthesis in a platform-based design approach. In [1] a multiplexer/demultiplexer and FIFO-based interface architecture is used.…”

Section: Introductionmentioning

confidence: 99%

A design methodology for space-time adapter

Coussy¹,

Urard

Martin

2007

Proceedings of the 17th ACM Great Lakes Symposium on VLSI

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This paper presents a solution to efficiently explore the design space of communication adapters. In most digital signal processing (DSP) applications, the overall architecture of the system is significantly affected by communication architecture, so the designers need specifically optimized adapters. By explicitly modeling these communications within an effective graphtheoretic model and analysis framework, we automatically generate an optimized architecture, named Space-Time AdapteR (STAR). Our design flow inputs a C description of Input/Output data scheduling, and user requirements (throughput, latency, parallelism…), and formalizes communication constraints through a Resource Constraints Graph (RCG). The RCG properties enable an efficient architecture space exploration in order to synthesize a STAR component. The proposed approach has been tested to design an industrial data mixing block example: an Ultra-Wideband interleaver.

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“…In [10] authors propose to automatically generate simulation wrappers for MPSoC architectures. Based on communication templates, [7] presents a generic interface unit architecture for communication synthesis in a platform-based design approach. In [1] a multiplexer/demultiplexer and FIFO-based interface architecture is used.…”

Section: Introductionmentioning

confidence: 99%

A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver

Coussy¹,

Urard

Martin³

2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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ISBN:1-4244-0921-7International audienceThis paper presents a solution to efficiently explore the design space of communication adapters. In most digital signal processing (DSP) applications, the overall architecture of the system is significantly affected by communication architecture, so the designers need specifically optimized adapters. By explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named Space-Time AdapteR (STAR). Our design flow inputs a C description of Input/Output data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a Resource Constraints Graph (RCG). The RCG properties enable an efficient architecture space exploration in order to synthesize a STAR component. The proposed approach has been tested to design an industrial data mixing block example: an Ultra-Wideband interleaver

show abstract

A practical tool box for system level communication synthesis

Cited by 12 publications

References 8 publications

Constrained algorithmic IP design for system-on-chip

Constrained algorithmic IP design for system-on-chip

A design methodology for space-time adapter

A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver

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