A practical way to extend shared memory support beyond a motherboard at low cost

Montaner, Hector; Silla, Federico; Duato, J.

doi:10.1145/1851476.1851495

Cited by 7 publications

(2 citation statements)

References 16 publications

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“…Another approach highly similar to DeACT is that taken by MEMSCALE [90], [91]. Like DeACT, MEMSCALE introduces a modified memory controller that can access the memory of other nodes over the HyperTransport protocol.…”

Section: D: Other Hardware Modificationsmentioning

confidence: 99%

Disaggregated Memory in the Datacenter: A Survey

Ewais

Chow

2023

IEEE Access

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Datacenters of today have maintained the same architecture for decades. The building block of the datacenter remains the server, which tightly couples the necessary compute resources, memory, and storage to run its tasks. However, this traditional approach suffers from under-utilization of its resources, often caused by the over-provisioning of these resources when deploying applications. Datacenter operators allocate the worst-case amount of memory required for each deployed application, which lasts for the entirety of the application's lifetime, even when not actually used. This causes servers to quickly, and falsely, run out of memory before their CPUs have been fully utilized. To address these problems, a new shift in the way datacenters are being built has been gaining more traction. Namely, memory disaggregation. Memory disaggregation can address these problems by decoupling the computational elements from the memory resources, allowing each to be provisioned and utilized separately. While the idea of memory disaggregation is not new, an increasing number of different proposals of memory disaggregation have seen the light in recent years. In this paper, we review many of these recent proposals, and study their architectures, implementations, and requirements. We also categorize them based on their features, and attempt to identify their strengths and shortcomings in an effort to highlight possible directions for future work and provide a reference for the research community.

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Section: D: Other Hardware Modificationsmentioning

confidence: 99%

Disaggregated Memory in the Datacenter: A Survey

Ewais

Chow

2023

IEEE Access

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“…Earlier disaggregated designs used virtual memory disaggregation by sharing memory between server nodes at rack-scale, wherein non-transparent PCIe switches were used to provide unified view of memory [10][11][12][13]. Although it allowed both cache-based load/store and RDMA-based paged access to remote memory, PCIe interconnects suffer from low memory bandwidth.…”

Section: Related Work and Motivationmentioning

confidence: 99%

Design, Modeling, and Analysis of Memory Allocation Policies for Rack-Scale Memory Disaggregation

Puri

Jose

Tamarapalli

2023

Preprint

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Memory disaggregation architecture is an emerging alternative to the traditional server architecture to address the issue of memory under-utilization in data centers. Memory disaggregation offers a large pool of remote memory connected via high-speed network fabric, thereby allows independent upgrade of memory components. Disaggregated design gives better adaptability of servers to the ever-increasing memory requirement from applications, such as HPC workload, video and big data analytics. However, disaggregrated memory architectures cause significantly large memory access latency due to the limited speed of interconnects currently used. In this paper, we propose a rack-scale disaggregated memory architecture and discuss the various software/hardware design aspects for such an architecture. We analyze the remote memory access latency in this architecture and observe that a significant part of the latency arises out of not only the interconnect, but also due to the contention at the queues of remote memory. To address this issue, we propose two-phase memory allocation policies for disaggregated memory environments that could significantly reduce the average memory access latency, compared to the conventional policies. We built a simulator that uses a trace-based front-end module and a cycle-accurate memory simulator to evaluate the memory access latency in a disaggregated memory system. We conduct experiments with different allocation policies across various benchmarks, representing applications with diverse memory access patterns. Our study shows encouraging results toward adoption of rack-scale memory disaggregation with acceptable memory latency, that could further be reduced with other system-level optimizations.

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