A preliminary architecture for a basic data-flow processor

Dennis, Jack B.; Misunas, David P.

doi:10.1145/285930.286058

Cited by 170 publications

(86 citation statements)

References 3 publications

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“…Most research cites the original definition of a DataFlow machine in 1975 by Jack Dennis at MIT [11]. The goal was to achieve instruction level parallelism and implementations derived from this concept were all based on the dataflow graph of a program, but differed in details such as the number of tokens that could be present on each dataflow graph edge, and whether execution could begin before all tokens were present.…”

Section: Dataflow Machines 1) Historymentioning

confidence: 99%

“…For example, original focus of data flow machines [11] was fine grain instruction parallelism, JavaFlow offers an easily repeatable design structure where selected elements can be powered off. While instruction level parallelism may be achieved, the automatic management of method loading and the potentially longer hops between nodes may detract from instruction parallelism.…”

Section: ) Trips and Wavescalarmentioning

confidence: 99%

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Extreme multi-core, multi-network Java DataFlow Machine (JavaFlow)

Ascott

Swartzlander

2015

2015 49th Asilomar Conference on Signals, Systems and Computers

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JavaFlow, is an extreme multi-core, multinetwork DataFlow Machine implementing a Java Virtual Machine aimed at addressing technology roadmap issues with the ability to effectively utilize and manage large numbers of processing cores. Specific design challenges addressed include: design complexity through a common set of repeatable structures; low power and reliability by featuring unused circuits and ability to power off or bypass sections of the chip; and clock propagation and wire limits by using locality to bring data to processing elements. A static Data Flow Architecture is used with multiple heterogeneous networks to connect processing elements capable of executing a single Java ByteCode instruction. Whole methods are cached in this DataFlow fabric, and the networks plus distributed intelligence are used for their management and execution. Analysis of SPEC JVM benchmarks demonstrates the potential for this design concept.A baseline configuration is defined with a compressed dataflow structure and then compared to multiple configurations of instruction assignments and clock relationships. Using a series of methods from the SPEC benchmark running independently, IPC (Instructions per Cycle) performance of the sparsely populated heterogeneous structure is 40% of the baseline. The average ratio of instructions to required nodes is 3.1. Innovative solutions to the loading and management of Java methods along with the translation from control flow to DataFlow structure are demonstrated.

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Section: Dataflow Machines 1) Historymentioning

confidence: 99%

Section: ) Trips and Wavescalarmentioning

confidence: 99%

Extreme multi-core, multi-network Java DataFlow Machine (JavaFlow)

Ascott

Swartzlander

2015

2015 49th Asilomar Conference on Signals, Systems and Computers

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“…We derive this taxonomy through analysis of the excellent review of different dataflow architectures presented in [5]. Static dataflow architectures permit only a single instance of the graph to be active in hardware at any given time, greatly simplifying the hardware design [3]. Dynamic dataflow machines [4], [12] allow multiple instances of the same dataflow graph to be active at the same time, complicating the token tracking hardware but generalizing the applicability.…”

Section: A Dataflow Organization Taxonomymentioning

confidence: 99%

Limits of Statically-Scheduled Token Dataflow Processing

Kapre

Siddhartha

2014

2014 Fourth Workshop on Data-Flow Execution Models for Extreme Scale Computing

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FPGA-based token dataflow processing has been shown to accelerate hard-to-parallelize problems exhibiting irregular dataflow parallelism by as much as an order of magnitude when compared to conventional compute organizations. However, when the structure of the dataflow computation is known upfront, either at compile time or at the start of execution, we can employ static scheduling techniques to further improve performance and enhance compute density of the dataflow hardware. In this paper, we identify the costs and performance trends of both static and dynamic scheduling approaches when considering hardware acceleration of SPICE device equations and Sparse LU factorization in circuit graphs. While the experiments are limited to a case study, the hardware design and dataflow compiler are general and can be extended to other problems and instances where dataflow computing may be applicable. With this study, we hope to develop a quantitative basis for the design of a hybrid dataflow architecture that combines both static and dynamic scheduling techniques. We observe a performance benefit of 2-4⇥ and a resource utilization saving of 2-3⇥ in favor of statically scheduled hardware.

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“…of various systems to achieve performance portability. The ability of multithreaded execution models with dataflow [8][9][10][11] roots to tolerate latencies and synchronization overheads, by switching dynamically between ready computation threads [12], has made it the model of choice for designing parallel programming models, APIs, compilation strategies, and runtime system software to achieve performance portability across different parallel architectures.…”

Section: Introductionmentioning

confidence: 99%

Performance portability on EARTH: a case study across several parallel architectures

2007

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Due to the increase of the diversity of parallel architectures, and the increasing development time for parallel applications, performance portability has become one of the major considerations when designing the next generation of parallel program execution models, APIs, and runtime system software. This paper analyzes both code portability and performance portability of parallel programs for finegrained multi-threaded execution and architecture models. We concentrate on one particular event-driven fine-grained multi-threaded execution model-EARTH, and discuss several design considerations of the EARTH model and runtime system that contribute to the performance portability of parallel applications. We believe that these are important issues for future high end computing system software design. Four representative benchmarks were conducted on several different parallel architectures, including two clusters listed in the 23rd supercomputer TOP500 list. The results demonstrate that EARTH based programs can achieve robust performance portability across the selected hardware platforms without any code modification or tuning.

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A preliminary architecture for a basic data-flow processor

Cited by 170 publications

References 3 publications

Extreme multi-core, multi-network Java DataFlow Machine (JavaFlow)

Extreme multi-core, multi-network Java DataFlow Machine (JavaFlow)

Limits of Statically-Scheduled Token Dataflow Processing

Performance portability on EARTH: a case study across several parallel architectures

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