A preliminary architecture for a basic data-flow processor

Dennis, Jack B.; Misunas, David P.

doi:10.1145/642089.642111

Cited by 194 publications

(50 citation statements)

References 2 publications

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“…As in other dataflow architectures, a program is represented as a dataflow graph and instruction dependencies are explicit [7][8]. There is no program counter, instructions are fetched and placed on the grid as they are required.…”

Section: Overview Of Target Tiled Dataflow Machine: Wavescalarmentioning

confidence: 99%

Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures

Farooq

John

Jacome

2009

High Performance Embedded Architectures and Compilers

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Abstract. Traditional predicated execution uses two techniques: top predication -in which only the head of the dependence chain is predicated, and bottom predication -in which only the tail of the dependence chain is predicated. Top predication prevents speculative execution, thus delivering minimum performance at minimum energy cost, while bottom predication allows full speculation of the dependence chain, resulting in maximum performance at maximum energy cost. In this paper, we propose a novel power-aware ILP extraction technique, denoted the 'elasticblock', that combines these two extremes, exposing superior energy vs. performance trade-offs. Each instruction in the elastic-block is explicitly guarded by two predicates: the speculative, and the final. Instruction's final predicate is generated using traditional if-conversion technique, while the speculative predicate has its default value statically assigned by the compiler, enabling it to make power-performance trade-offs in the code. Several energy saving code optimizations are proposed for the elasticblock structure.

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Section: Overview Of Target Tiled Dataflow Machine: Wavescalarmentioning

confidence: 99%

Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures

Farooq

John

Jacome

2009

High Performance Embedded Architectures and Compilers

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“…which returns the list (2,6,24). In this example it is assumed that if , =, * , −, pair, head, tail, nil and the integers are elements of Con.…”

Section: Preliminariesmentioning

confidence: 99%

“…Using a language such as Alfl allows one to write the semantic equations almost verbatim from their denotational form. 6 An interesting future research project is to integrate the interpreter into a real-time graphical environment that allows one to see the execution tree unfold dynamically.…”

Section: Commentarymentioning

confidence: 99%

“…This is in contrast to more conventional languages, where explicit constructs are typically used to invoke, synchronize, and in general coordinate the concurrent activities. Many of the earlier functional languages were in fact developed simultaneously with work on highly-parallel dataflow and reduction machines [1,5,6,17], and such research continues today (see [11,12,15] and the survey in [22]). In all of these efforts the parallelism in a program is detected by the system and allocated to processors automatically.…”

Section: Introductionmentioning

confidence: 99%

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Denotational semantics of a para-functional programming language

Hudak

1986

Int J Parallel Prog

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A para-functional programming language is a functional language that has been extended with special annotations that provide an extra degree of control over parallel evaluation. Of most interest are annotations that allow one to express the dynamic mapping of a program onto a known multiprocessor topology. Since it is quite desirable to provide a precise semantics for any programming language, in this paper a denotational semantics is given for a simple para-functional programming language with mapping annotations. A precise meaning is given not only to the normal functional behavior of the program (i.e., the answer), but also to the operational notion of where (i.e., on what processor) expressions are evaluated. The latter semantics is accomplished through an abstract entity called an execution tree.

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“…They generally implement on the fly only a small, dynamically changing window of dataflow execution. Under the pure data-driven (dataflow ) model/paradigm of computation, an instruction is executed as soon as all its operands become available [2]. Instructions are not ordered and also carry with them their operands.…”

Section: Introductionmentioning

confidence: 99%

Dataflow computation with intelligent memories emulated on field-programmable gate arrays (FPGAs)

Ingersoll¹,

Ziavras²

2002

Microprocessors and Microsystems

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This paper presents a new design that implements the data-driven (i.e. dataflow) computation paradigm with intelligent memories. Also, a relevant prototype that employs FPGAs is presented for the support of intelligent memory structures. Instead of giving the CPU the privileged right to decide what instructions to fetch in each cycle (as is the case for control-flow CPUs), instructions in dataflow computers enter the execution unit on their own when they are ready to execute. This way, the application-knowledgeable algorithm, rather than the applicationignorant CPU, is in control. This approach could eventually result in outstanding performance and elimination of large numbers of redundant operations that plague current control-flow designs. Control-flow and dataflow machines are two extreme computation paradigms. In their pure form, the former machines follow an inherently sequential execution process while the latter are parallel in nature. The sequential nature of control-flow machines makes them relatively easy to implement compared to dataflow machines, which have to address a number of issues that are easily solved in the realm of the control-flow paradigm. Our dataflow design solves these issues at the intelligent memory level, separating the processor from dataflow maintenance tasks. It is shown that using intelligent memories with basic components similar to those of FPGAs produces a feasible approach. Expected improvements within the next few years in underlying intelligent memory and FPGA technologies will have the potential to make the effect of our approach even more dramatic. q

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A preliminary architecture for a basic data-flow processor

Cited by 194 publications

References 2 publications

Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures

Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures

Denotational semantics of a para-functional programming language

Dataflow computation with intelligent memories emulated on field-programmable gate arrays (FPGAs)

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