A Programmable Hyper-Dimensional Processor Architecture for Human-Centric IoT

Datta, Sohum; Antonio, Ryan Albert G.; Ison, Aldrin R. S.; Rabaey, Jan M.

doi:10.1109/jetcas.2019.2935464

Cited by 60 publications

(29 citation statements)

References 54 publications

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“…There are also fields where the research on PNNs should focus on, such as the Hyper dimensional Learning (HL) [106], [107], a modern and very promising approach to NNs, which is still the development stage. Here, the problem of a photonic materialization lies in the very big size of the internal representation of objects that are used in HL.…”

Section: Conclutionsmentioning

confidence: 99%

A Comprehensive Survey on Nanophotonics Neural Networks

Demertzis¹,

Παπαδόπουλος²,

Iliadis³

et al. 2021

Preprint

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: In the last years, materializations of neuromorphic circuits based on nanophotonic arrangements have been proposed, which contain complete optical circuits, laser, photodetectors, photonic crystals, optical fibers, flat waveguides, and other passive optical elements of nanostructured materials, which eliminate the time of simultaneous processing of big groups of data, taking advantage of the quantum perspective and thus highly increasing the potentials of contemporary intelligent computational systems. This article is an effort to record and study the research that has been conducted concerning the methods of development and materialization of neuromorphic circuits of Neural Networks of nanophotonic arrangements. In particular, an investigative study of the methods of developing nanophotonic neuromorphic processors, their originality in neuronic architectural structure, their training methods and their optimization has been realized along with the study of special issues such as optical activation functions and cost functions.

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Section: Conclutionsmentioning

confidence: 99%

A Comprehensive Survey on Nanophotonics Neural Networks

Demertzis¹,

Παπαδόπουλος²,

Iliadis³

et al. 2021

Preprint

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“…Prior work has proposed various algorithmic and hardware innovations to tackle the computational challenges of HD. Acceleration in hardware has typically focused on FPGAs [16][17][18] or ASIC-ish accelerators [19,20]. FPGA-based implementations provide high parallelism and bit-level granularity of operations that significantly improves the effective utilization of resources and performance.…”

Section: Motivationmentioning

confidence: 99%

“…This flexibility is crucial since learning applications are heterogeneous in practice. Therefore, we here focus on an FPGA based implementation but emphasize our techniques are generic and can be integrated with ASIC- [19] and processor-based [20] implementations. As noted in the preceding section, the element-wise sum is a critical operation in the encoding pipeline.…”

Section: Motivationmentioning

confidence: 99%

SHEAR er

Khaleghi

Salamat

Thomas

et al. 2020

Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design

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Hyperdimensional computing (HD) is an emerging paradigm for machine learning based on the evidence that the brain computes on highdimensional, distributed, representations of data. The main operation of HD is encoding, which transfers the input data to hyperspace by mapping each input feature to a hypervector, followed by a bundling procedure that adds up the hypervectors to realize the encoding hypervector. The operations of HD are simple and highly parallelizable, but the large number of operations hampers the efficiency of HD in embedded domain. In this paper, we propose SHEAR , an algorithmhardware co-optimization to improve the performance and energy consumption of HD computing. We gain insight from a prudent scheme of approximating the hypervectors that, thanks to error resiliency of HD, has minimal impact on accuracy while provides high prospect for hardware optimization. Unlike previous works that generate the encoding hypervectors in full precision and then and then perform ex-post quantization, we compute the encoding hypervectors in an approximate manner that saves resources yet affords high accuracy. We also propose a novel FPGA architecture that achieves striking performance through massive parallelism with low power consumption. Moreover, we develop a software framework that enables training HD models by emulating the proposed approximate encodings. The FPGA implementation of SHEAR achieves an average throughput boost of 104,904× (15.7×) and energy savings of up to 56,044× (301×) compared to state-of-the-art encoding methods implemented on Raspberry Pi 3 (GeForce GTX 1080 Ti) using practical machine learning datasets.

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“…Authors in [26] propose a memory-centric architecture for the HD classifier with modular and scalable components, and demonstrate its performance on a language identification task. In [27], authors develop a programmable and scalable architecture for energyefficient supervised classification using HD computing, and compare it with traditional architectures for a few conventional machine learning algorithms. The work in [28] explores architectural designs for the cleanup memory to facilitate energy-efficient, fast, and scalable search operation, and the proposed designs are evaluated for a language recognition application.…”

Section: Related Workmentioning

confidence: 99%