A Pseudo-Virtual Ground Feedforwarding Technique Enabling Linearization and Higher Order Noise Shaping in VCO-Based ΔΣ Modulators

Pochet, Corentin; Hall, Drew A.

doi:10.1109/jssc.2022.3202040

Cited by 8 publications

(2 citation statements)

References 31 publications

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“…This alters the comparator threshold leading to a false decision. That is, if the previous output state is H, the actual threshold becomes lower than the nominal threshold, once the output state changes back to L and vice versa when the previous output state is L. Furthermore, the amount of hysteresis is provided as: Hystresis = V TH − V TL (6) where V TH and V TL is the upper and lower threshold of the comparator, respectively. Figure 5 shows the comparator macro model, where the DD pre-amp.…”

Section: Comparator Macro Modelmentioning

confidence: 99%

“…Since the concept of the sigma-delta modulator was first proposed in 1962 [4], sigma-delta modulators have evolved due to the increased demands on higher bandwidth and resolution. In particular, multi-bit quantizers [5], higher order modulators [6], multi-stage noise shaping (MASH) structures [7], and time-interleaved architectures [8] have been realized to extend the bandwidth and resolution. However, due to the oversampling nature of sigma-delta modulators, even with the above-mentioned improvements, the high sampling rate is the main obstacle that leads to long simulation time.…”

Section: Introductionmentioning

confidence: 99%

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Macro Model for Discrete-Time Sigma‒Delta Modulators

Lee

2022

Electronics

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This work presents a macro model for discrete-time sigma‒delta modulators, which can significantly reduce the simulation time compared to transistor level circuits. The proposed macro model is realized by effectively combining active and passive ideal circuit components with Verilog-A modules. As such, since the macro model is a true representation of the actual transistor level circuit, a moderately good accuracy can be obtained. In addition, the proposed macro model includes the major amplifier, comparator, and switch‒capacitor non-idealities of the sigma‒delta modulator such as amplifier DC gain, GBW, slewrate, comparator bandwidth, hysteresis, parasitic capacitance, and switch-on resistance. The results show the simulation time of the proposed macro model sigma‒delta modulator is only 6.43% of the transistor level circuit with comparable accuracy. As a result, the proposed macro model can facilitate the circuit design and leverage non-ideality analysis of discrete-time sigma‒delta modulators. As a practical design example, a second order discrete-time sigma‒delta modulator with a five-level quantizer is realized using the propose macro model for GSM and WCDMA applications.

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Section: Comparator Macro Modelmentioning

confidence: 99%