A radiation tolerant Phase Locked Loop design for digital electronics

Kumar, Rajesh; Karkala, Vinay; Garg, Rajesh; Jindal, Tanuj; Khatri, Sunil P.

doi:10.1109/iccd.2009.5413108

Cited by 12 publications

(6 citation statements)

References 26 publications

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“…Radiation Hardening by Design: There has been a great deal of work on radiation hardened circuit design approaches. Rajesh [11] proposed a radiation hard PLL designed using 65nm CMOS process using circuit level hardening approach. It utilizes two independent charge pump/ low pass filter blocks, which drive two separate VCOs.…”

Section: A Previous Related Workmentioning

confidence: 99%

RHBD Charge Pump PLL based 2.4 GHz Frequency Synthesizer

Prasad¹,

Sandya²

2019

IJRTE

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Frequency Synthesizer forms the heart of electronic communication system. Phase Locked Loop (PLL) based Frequency Synthesizers over the years has become the ubiquitous solution for generation of stable clock source. But it is a challenging task to design and develop PLL to be used in radiation environment such as in satellites, space systems and military electronics. Since impact of radiation strike on PLL is said to introduce transient faults resulting in increased timing jitter, distortion in phase, and bit flips. One or more of the above said effects can initiate false triggering which may result in incorrect data to be latched, loss of synchronization in data processing and networking. This may lead to catastrophic effect. Hence, as the stability of frequency synthesizer is of vital importance, there is a stressful need for design of radiation hard, fault tolerant frequency synthesizer. With this motivation, in this paper, a radiation hard CMOS Charge Pump PLL is designed to synthesize a 2.4GHz frequency source using 20MHz reference input frequency. The proposed radiation hard PLL design uses a hybrid Radiation Hardening By Design (RHBD) fault tolerant technique combined with redundancy, hence offering a twofold level of fortification from radiation spikes. Cadence tool was used for simulation. The PLL designed has exhibited satisfactory performance. The RHBD Charge Pump PLL in presence of radiation strike resulted in rms jitter of 128.9ps, phase noise of -94.03dbc/Hz and settling time of 159ns against the IEEE 802.11b/g standard requirement of 250ps jitter, -110dbc/Hz phase noise and 10us setting time.

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Section: A Previous Related Workmentioning

confidence: 99%

RHBD Charge Pump PLL based 2.4 GHz Frequency Synthesizer

Prasad¹,

Sandya²

2019

IJRTE

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“…To find out the frequency of oscillation of VCO, total delay offered by inverters is desired. The total delay offered by inverters can be calculated by finding the capacitance offered by one inverter [8][9][10][11][12][13][14].…”

Section: Current-starved Vco Designmentioning

confidence: 99%

Modelling and mitigation of single-event upset in CMOS voltage-controlled oscillator

et al. 2018

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Single-event effects (SEEs) have been the primary concern in study of radiation effects since late 1970s with the discovery of soft errors in terrestrial and space environments. The interaction of a single ionized particle with electronic devices leads to SEEs. In this paper, single-event upset (SEU) on CMOS devices in designing of a voltage-controlled oscillator (VCO) is analysed. Further, mitigation approaches of SEU are also discussed. To observe the impact of radiation, a VCO was designed in Cadence Virtuoso, and GDSII file of one ring oscillator stage was extracted to incorporate the same design in Silvaco MaskViews. With the help of layer map information file, masks were identified and used to design the CMOS inverter structure file for simulation of SEU condition. The input parameters for SEU simulation were evaluated from linear energy transfer (LET) graph of heavy ion under space conditions. The current profile of CMOS inverter was extracted under influence of a high-energy particle with the help of LET graph of that particle. This current profile was applied to different nodes of VCO and upset conditions were identified. Further, the impact of upset conditions on lock stage of phase-locked loop (PLL) is discussed. Results show that the SEU has significant impact on the logic state of inverters used in ring oscillator stage compared with current starving/biasing stage. The current profile of CMOS device has strong dependence on the energy of ion, its track, angle of incidence and the material. When angle of incidence is very less (7 À 14) the channel will be occupied by a funnel of charge and it leads to the maximum degradation of device. This work shows that a device operating at high frequency is more susceptible to SEU. Triple modular redundancy (TMR) and Radiation Hardened By Design (RHBD) can be used to mitigate SEU. TMR consumes more power and is less accurate compared with the RHBD approach.

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“…RHBD techniques using two CP, loop filter (LF) and cross-coupled VCO have been introduced in [12,13]. Figure 1 shows the architecture of previous PLL using RHBD techniques.…”

Section: Introductionmentioning

confidence: 99%

A radiation-hardened-by-design phase-locked loop using feedback voltage controlled oscillator

Jung

Roveda

2015

Sixteenth International Symposium on Quality Electronic Design

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This paper presents a radiation-hardened-by-design (RHBD) phase-locked loop (PLL) which utilizes a feedback voltage controlled oscillator (FBVCO) to mitigate a single event transient (SET) strike. Whenever the SET pulse attacks the input control voltage of VCO, VCO gives rise to a frequency disturbance and PLL produces a huge jitter at the output clock. The proposed FBVCO consists of an open loop VCO, an integrator and a switched-capacitor resistor. The input transfer function of the FBVCO has a low-pass characteristic so that the FBVCO can reduce any perturbation at the input control voltage. In addition, the proposed RHBD PLL reduces size by using one loop filter (LF) and charge pump (CP) compared to prior works. We simulate the proposed scheme in 130 nm low power CMOS technology at 1.5V supply. The output frequency variation of the proposed PLL from the SET strike is 75% smaller than that of previous PLL at 300 MHz. This RHBD PLL consumes 6.2 mW at 400 MHz output frequency. KeywordsPhase-locked loop (PLL), radiation-hardened-by-design (RHBD), voltage controlled oscillator (VCO), loop filter (LF)

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A radiation tolerant Phase Locked Loop design for digital electronics

Cited by 12 publications

References 26 publications

RHBD Charge Pump PLL based 2.4 GHz Frequency Synthesizer

RHBD Charge Pump PLL based 2.4 GHz Frequency Synthesizer

Modelling and mitigation of single-event upset in CMOS voltage-controlled oscillator

A radiation-hardened-by-design phase-locked loop using feedback voltage controlled oscillator

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