A Re-Use Methodology for Formal SoC Protocol Compliance Verification

Nguyen, Minh D.; Thalmaier, Max; Wedler, Markus; Stoffel, Dominik; Kunz, Wolfgang; Bormann, Jörg

doi:10.1007/978-90-481-9304-2_12

Cited by 3 publications

(2 citation statements)

References 6 publications

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“…Model checking techniques are used for Serial Peripheral Interface (SPI) protocol compliance verification in [7]. Here the Compliance Test Language (CTL) language is used to specify the protocol properties.…”

Section: Related Workmentioning

confidence: 99%

Design of SD/eMMC Protocol Compliance Solutions

Aparna¹,

Mamatha²,

Tomar³

et al. 2014

IJAIS

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Protocol Validation is an important step in validating the I/O interface of the System on Chip (SoC). In developing the protocol compliance solutions for validating the Secure Digital/Embedded Multi Media Controller (SD/eMMC) protocol, the main intention is to capture the behavior of protocol under various physical conditions using a Logic Analyzer (LA). LA facilitates more capture of data and offers more number of channels and is more cost effective compared to existing Digital Storage Oscilloscope (DSO) methodology. In addition to decode, the solution is capable of carrying out the analysis of the data captured and decoded from LA. Analysis functionality includes command-response analysis, cyclic redundancy check, integrity check and flow analysis that assess and reports the functionality and performance of the protocol under variations of temperature & voltage conditions. Analyzer helps in tracing out all kind of deviations from the specifications and standards defined for SD and eMMC.

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Section: Related Workmentioning

confidence: 99%

Design of SD/eMMC Protocol Compliance Solutions

Aparna¹,

Mamatha²,

Tomar³

et al. 2014

IJAIS

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“…The generation has also been automated in [7]. In contrast, formal methods have been used to prove the protocol correctness in a mathematical sense [8], [9], [10]. But all these approaches can not be applied at TLM.…”

Section: Introductionmentioning

confidence: 99%

TLM protocol compliance checking at the Electronic System Level

Bawadekji

Große

Drechsler

2011

14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems

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Abstract-Design and verification of embedded systems at the Electronic System Level (ESL) is common practice. In particular, Transaction Level Modeling (TLM) is the major reason for the success of ESL design. However, when detailed protocols are modeled at lower levels of TLM, the verification of the communication becomes a critical issue. In this paper, we present an approach for protocol compliance checking of new or detailed protocol implementations. They are checked against user-specified protocol sequences. We also analyze the protocol coverage achieved by the testbench and visualize the results on a protocol sequence graph. Experimental results for a SoC model demonstrate the advantages of our method.

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