A reconfigurable data-driven ALU for Xputers

Hartenstein, Reiner W.; Kress, Rainer; Reinig, Helmut

doi:10.1109/fpga.1994.315602

Cited by 17 publications

(8 citation statements)

References 6 publications

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“…The importance of this migration will be emphasized by the normally unsolved explosion of communication switches in the classical massively parallel computer systems. Frequently measured speed-up factors (in the extreme case more than 3 orders of magnitude) show, that d-processors are a promising universal platform [12], [38], [55], [60] - [68].…”

Section: Figure 9 Comparisons Of Different Computing Paradigmsmentioning

confidence: 99%

<title>Codesign and high-performance computing: scenes and crisis</title>

et al. 1996

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Section: Figure 9 Comparisons Of Different Computing Paradigmsmentioning

confidence: 99%

<title>Codesign and high-performance computing: scenes and crisis</title>

et al. 1996

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“…The reconfigurable arithmetic and logic unit (rALU) consists of a regular array of identical processing elements called datapath units (DPUs) [9]. Each DPU has two input and two output registers.…”

Section: Reconfigurable Arithmetic and Logic Unitmentioning

confidence: 99%

<title>Reconfigurable machine for applications in image and video compression</title>

Hartenstein

Becker

Kress

et al. 1995

Advanced Image and Video Communications and Storage Technologies

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This paper presents a reconfigurable machine for applications in image or video compression. The machine can be used stand alone or as a universal accelerator co-processor for desktop computers for image processing. It is well suited for image compression algorithms such as JPEG for still pictures or for encoding MPEG movies. It provides a much cheaper and more flexible hardware platform than special image compression ASICs and it can substantially accelerate desktop computing.

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“…The rALU is based on field-programmable logic (FPL). In the MoM the reconfigurable datapath architecture (rDPA) is used, an FPL architecture with better throughput and higher area efficiency than FPL available commercially [6]. The (re-)configuration of GAGs and rALU subnets is done by a special MoM-3 controller circuit (M3C).…”

Section: The Map-oriented Machinementioning

confidence: 99%

“…Partitioning of the statements onto the different rDPA chips is not necessary since the array of rDPA chips appears as one array of DPUs with transparent chip boundaries [6].…”

Section: Ralu Synthesismentioning

confidence: 99%