A regular representation for mapping to fine-grain, locally-connected FPGAs

Chrzanowska-Jeske, M.; Wang, Zhi; Xu, Yang

doi:10.1109/iscas.1997.612894

Cited by 22 publications

(24 citation statements)

References 6 publications

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“…A particularly important open problem is to define generic recursive butterfly diagrams to create all expansion polarities of certain practical types and for arbitrary numbers of variables. A very practical application of the methods presented and outlined here is for the optimization of various types of lattice diagrams [14,17,19,25,31,32], such as regular lattices with two, three and especially four inputs/outputs from a node. All methods can be applied to new Xilinx FPGAs, as well as to similar lookup-table architectures.…”

Section: Discussionmentioning

confidence: 99%

Efficient Algorithms for Creation of Linearly‐independent Decision Diagrams and their Mapping to Regular Layouts

et al. 2000

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A new kind of a decision diagrams are presented: its nodes correspond to all types of nonsingular expansions for groups of input variables, in particular pairs. The diagrams are called the Linearly Independent (LI) Decision Diagrams (LI DDs). There are 840 nonsigular expansions for a pair of variables, thus 840 different types of nodes in the tree. Therefore, the number of nodes in such (exact) diagrams is usually much smaller than the number of nodes in the well-known Kronecker diagrams (which have only single-variable Shannon, Positive Davio, and Negative Davio expansions in nodes). It is usually much smaller than 1/3 of the number of nodes in Kronecker diagrams. Similarly to Kronecker diagrams, the LI Diagrams are a starting point to a synthesis of multilevel AND/OR/EXOR circuits with regular structures. Other advantages of LI diagrams include: they generalize the well-known Pseudo-Kronecker Functional Decision Diagrams, and can be used to optimize the new type of PLAs called LI PLAs. Importantly, while the known decision diagrams used AND/EXOR or AND/OR bases, the new diagrams are AND/OR/EXOR-based. Thus, because of a larger design space, multi-level structures of higher regularity can be created with them. This paper presents both new concepts and new efficient synthesis algorithms.

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Section: Discussionmentioning

confidence: 99%

Efficient Algorithms for Creation of Linearly‐independent Decision Diagrams and their Mapping to Regular Layouts

et al. 2000

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“…The reintroduction of a variable makes it necessary to use the same expansion variable more than once which increases the number of levels. Such diagrams are called PSBDDs with repeated variables and are discussed in details in [6]. The delay of such structures is proportional to a number of levels in a diagram, which is always larger than a number of function variables.…”

Section: Ivpsbddsmentioning

confidence: 99%

“…The delay of such structures is proportional to a number of levels in a diagram, which is always larger than a number of function variables. A number of variables which have to be repeated depends very strongly on an order of decomposition variables and various order optimization algorithms were developed [6]. …”

Section: Ivpsbddsmentioning

confidence: 99%

Regular symmetric arrays for non-symmetric functions

Chrzanowska-Jeske

ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349)

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A new class of non-totally symmetric functions which can be represented as simple regular symmetric arrays without redundancy is identified. Regular circuits are becoming crucialy important for deep submicron technologies, which needs new layout approaches to fully utilized their potential. The new class of functions contains the classes of totally symmetric and totally symmetric with mixed polarities functions Two circuit implementations are proposed, one especially aimed on low-power applications. Generating such functions with a simple method is also described.

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“…These approaches are mainly based on mapping Binary Decision Diagrams (BDDs) [5] to MUX f = :ifzi=o + zifzi=l (1 5 i < n) based FPGAs. Beside the pure synthesis aspect, also the testability of the resulting circuits has been studied Recently, a new design style based on Lattice Diagrams (LDs) has been proposed and successfully applied [18,9,20,8,16,151. LDs combine the synthesis and the layout step.…”

Section: Binary Decision Diagramsmentioning

confidence: 99%

Testability of circuits derived from lattice diagrams

Drechsler

Günther²,

Becker³

Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future

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I n this paper the testability of circuits derived from BDDs representing totally symmetric fmctions is analyzed. A test pattern generation technique is presented that has runtime linear in the size of the BDD. The result is directly applicable to circuits derived from lattice diagrams, a new design style that combines the synthesis and the layout step. Experimental results show that complete test generation for functions with more than 500 variables can be done in less than 1 CPU second.These results find direct application in the analysis of testability of LDs. Experimental results are given to demonstrate the efficiency of the approach.The paper is structured as follows: In Section 2 basic notation and definitions are reviewed. The testability results for totally symmetric functions are given in Section 3, and the application of these results to LDs is shown. Experiments are presented in Section 4 and finally the paper is summarized.

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A regular representation for mapping to fine-grain, locally-connected FPGAs

Cited by 22 publications

References 6 publications

Efficient Algorithms for Creation of Linearly‐independent Decision Diagrams and their Mapping to Regular Layouts

Efficient Algorithms for Creation of Linearly‐independent Decision Diagrams and their Mapping to Regular Layouts

Regular symmetric arrays for non-symmetric functions

Testability of circuits derived from lattice diagrams

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