A repairable and diagnosable cellular array on multiple-valued logic

Kamiura, Naotake; Hata, Yutaka; Yamato, K.

doi:10.1109/ismvl.1993.289575

Cited by 3 publications

(4 citation statements)

References 4 publications

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“…A useful perspective is to regard zero-maintenance as a multi-level design problem in similar fashion to the highly integrated nature of electronic systems design. An early analysis Time-shared redundancy [3] x x x [112] x x x [116] x x x ASIC (fine-grained) [82] x x x [117] x x x ASIC, (heterogeneous) [106] x x [118] x x [119] x x x [120] x x x FPGA implementations [99] x x x [121] x x x [122] x x x [123] x x x x…”

Section: B Hierarchical Perspectivementioning

confidence: 99%

Zero-maintenance of electronic systems: Perspectives, challenges, and opportunities

McWilliam

Khan

Farnsworth

et al. 2018

Microelectronics Reliability

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Self-engineering systems that are capable of repairing themselves in-situ without the need for human decision (or intervention) could be used to achieve zero-maintenance. This philosophy is synonymous to the way in which the human body heals and repairs itself up to a point. This article synthesises issues related to an emerging area of self-healing technologies that links software and hardware mitigations strategies. Efforts are concentrated on built-in detection, masking and active mitigation that comprises self-recovery or self-repair capability, and has a focus on system resilience and recovering from fault events. Design techniques are critically reviewed to clarify the role of fault coverage, resource allocation and fault awareness, set in the context of existing and emerging printable/nanoscale manufacturing processes. The analysis presents new opportunities to form a view on the research required for a successful integration of zero-maintenance. Finally, the potential cost benefits and future trends are enumerated.

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Section: B Hierarchical Perspectivementioning

confidence: 99%

Zero-maintenance of electronic systems: Perspectives, challenges, and opportunities

McWilliam

Khan

Farnsworth

et al. 2018

Microelectronics Reliability

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“…18 In this case, entire processing units are disabled in the event of a fault being detected and a reconfiguration of process scheduling occurs that is coordinated by the CA. A comparison of similar strategies was provided by Kamiura et al 19 where, again, the subjects were processors and permanent faults were handled by reconfiguration.…”

Section: Design Frameworkmentioning

confidence: 99%

Creating self-configuring logic with built-in resilience to multiple-upset events

McWilliam

Schiefer

Purvis

2015

Proceedings of the Institution of Mechanical Engineers, Part B:

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Electronic systems are prone to failures, whether during manufacture or throughout their in-service lifetime. A number of design and fabrication techniques are presently employed that maintain an economical production yield. However, the cost of through-life maintenance and fault mitigation operations for complex, high-value systems remains a major challenge and requires new design methods in order to increase their resilience. In this article, the focus is on applications that are sensitive to transient random errors caused by single-event upsets and multiple-bit upsets occurring within their electronic systems and sub-systems, as well as applications that benefit from fault detection and localisation. A novel self-restoration strategy is proposed based on a two-layer design approach comprising a fault-tolerant coordination layer with convergent cellular automata and a configurable functional logic layer. This design strategy is able to self-reconstruct the correct functional logic configuration in the event of transient faults without external intervention. The necessary convergent cellular automata rule set and state table sizes for 3 3 3 and 4 3 4 binary coded patterns are analysed in order to estimate the generic resource requirements for larger designs. Additionally, the possibility of exploiting the design for built-in fault detection and diagnostic reporting is investigated.

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“…In the binary arrays [4][5] and our array, our array requires the fewest cells for 1128. In the k-valued arrays[61 [10] and our array, our array also requires the fewest cells for n23.…”

Section: Fig3 the Linear Array Realizing F(am Xn)mentioning

confidence: 99%

“…The evaluation of the three types for the design, the fault tolerance, and the testability for multiple faults c l d i e s that the two-level array is the most suitable structure among the three types. Finally, we compare our fault-tolerant two-level array with formerly presented arrays[41- [10] to demonstrate the advantages of our array.…”

Section: : Introductionmentioning

confidence: 99%

Design of fault-tolerant cellular arrays on multiple-valued logic

Kamiura

Hata

Yamato

Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)

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This paper discusses the problems of the design and the fault tolerance in multiple-valued cellular arrays by considering the single-level array, the two-level array and the three-level array. These arrays are constructed by some cells that have the unique switch operation. It assumes the stuck-at-0 fault and the stuck-at-(k-I) fault of the switch cells on k-valued cellular arrays. The faulttolerant arrays for the single fault are constructed by building a duplicate row and a duplicate column iteratively in the arrays. By evaluating three types for the design, the fault tolerance and the testability for multiple faults, it clarifies that the two-level array is the most suitable structure. Finally, the comparison with formerly presented arrays shows advantages for our fault-tolerant two-level array.

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A repairable and diagnosable cellular array on multiple-valued logic

Cited by 3 publications

References 4 publications

Zero-maintenance of electronic systems: Perspectives, challenges, and opportunities

Zero-maintenance of electronic systems: Perspectives, challenges, and opportunities

Creating self-configuring logic with built-in resilience to multiple-upset events

Design of fault-tolerant cellular arrays on multiple-valued logic

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