2022
DOI: 10.1109/ted.2022.3152977
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A Review of 3-Dimensional Wafer Level Stacked Backside Illuminated CMOS Image Sensor Process Technologies

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Cited by 13 publications
(2 citation statements)
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“…[26] and the image sensor [27] technologies, we can adopt the backside fabrication process. After the fabrication of Schottky barrier FDSOI FETs in Fig.…”
Section: Proposed Device and Simulation Approachmentioning
confidence: 99%
“…[26] and the image sensor [27] technologies, we can adopt the backside fabrication process. After the fabrication of Schottky barrier FDSOI FETs in Fig.…”
Section: Proposed Device and Simulation Approachmentioning
confidence: 99%
“…[1][2][3] Hence, three-dimensional stacked CMOS image sensors (3D-CISs) have been developed. 4,5 In a 3D-CIS, the pixel part and the pixel data processing function are manufactured on separate wafers, and the wafers are bonded by Cu-Cu hybrid bonding or through silicon via (Cu-TSV). [6][7][8] However, if the barrier layer formed between the wafers bonded by Cu-Cu hybrid bonding is insufficient to prevent the diffusion of Cu, there is a concern of cause Cu contamination.…”
mentioning
confidence: 99%