A SAR ADC with a higher precision bootstrap switch and highest split capacitor array

Abstract

The design of this paper is a 12bit SAR ADC,in order to optimize its performance and be able to achieve high accuracy, there are certain requirements for certain modules of the ADC. The design uses the bottom plate sampling, access to the common mode level Vcm on the upper pole plate of the DAC capacitor array is accessed by a higher precision bootstrap switch to reduce the non-linearity brought by the Vcm level access switch. By performing FFT simulation on the sampling points, it can be used at a sampling rate of 50Ms/s when the input signal frequency is 0.8301MHz and ENOB is 15.64bit. The capacitor array uses a combination of segmentation and splitting to greatly reduce the number of total capacitors, achieving only 188 unit capacitors, a 97.7% reduction in number compared to the conventional structure, for the entire ADC digital circuit The power consumption as well as the area of the ADC digital circuit has been significantly improved. The comparator uses a dynamic latching comparator to reduce power consumption while reducing the equivalent input noise of the comparator. The logic circuit uses dynamic SAR logic to control the analog-to-digital converter's successive comparisons. Sampling and analysis of the entire SAR ADC output achieves a valid bit count of 11.93 bits at a low frequency input signal of 0.1953MHz, enabling the conversion of a 12bit SAR ADC.