A Second-Order True-VCO ADC Employing a Digital Pseudo-DCO Suitable for Sensor Arrays

Abstract

This paper explores the implementation of a VCO-based ADC, achieving an ENOB of 12 bits with 1 MHz of a sampling rate in the audio bandwidth. The solution exploits the scalability and PVT invariance of a novel digital-to-frequency converter to reduce the size and consumed power. The architecture has been validated in a 130 nm CMOS technology node displaying a power consumption of 105.57 μW and a silicon footprint of 0.034 mm2 in a pseudo-differential configuration. Performance can be dynamically adjusted to trade off power consumption by resolution without changing the sampling rate. In addition, the proposed architecture benefits from multiple instantiations in the same SoC, making it particularly suitable for sensor array applications, such as biomedical sensors and spatial audio arrays.