A Self-Biased Charge-Transfer Sense Amplifier

Patil, S.; Wieckowski, Michael; Margala, Martin

doi:10.1109/iscas.2007.377985

Cited by 8 publications

(17 citation statements)

References 4 publications

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“…Fig. 6 evidently shows that only the proposed design can operate down to a of 0.9 V while [13], [9], and [8] cease to work at equal to 1.2, 1.3, and 1.3 V, respectively. Furthermore, at any supply voltage, the new design outperforms the rest with the smallest For example, at pF, pF and the load capacitor pF, its sensing delay is reduced to 25.8%, 20.3%, and 28.6% and its power consumption is decreased to 37.6%, 46.5%, and 24.9% as compared with [13], [9] and [8], respectively.…”

Section: Performance Comparisionsmentioning

confidence: 97%

“…The current-mode SAs, marked by the presence of the conventional current-conveyor [5], is insensitive to the and, hence, offers a higher sensing speed and consumes less power compared with the voltage-mode counterparts [5]. Over the last two decades, a number of current-mode SAs have been proposed, aiming at improving the sensing speed and the power consumption in the read operation of the SRAM [7]- [13]. Since all of these SA designs utilize the differential output currents of the current 1549-7747/$25.00 © 2008 IEEE conveyor, their improvement is only incremental.…”

Section: A Current-mode Sa and Its Derivativesmentioning

confidence: 99%

“…P4 and P5 act as a switch to connect the BLs to the DLs. The other 10 transistors (P6 -P10 and N1-N5) form a cross-coupled inverter which amplifies the small voltage difference on the DLs to the full CMOS logic levels [8], [9], [11], [13] and [14]. The new SA is unique in a way that it eliminated the current conveyor and transformed the normally-large BL loads (P0, P1 in Fig.…”

Section: A Circuit Operationmentioning

confidence: 99%

“…The proposed SA and other existing designs [8], [9], and [13] have been optimized and extensively simulated using Cadence's Affirma Spectre circuit simulator based on a 0.18-m CMOS process from CHRT. All four circuits were simulated using a simplified read-cycle-only two columns, two rows memory system.…”

Section: Performance Comparisionsmentioning

confidence: 99%

“…The operations and read effectiveness of the existing current-mode and the proposed SAs are described in Sections II and III, respectively. Sensing delay and power consumption of the new design are graphically presented in Section IV, in comparison with the three best existing designs, namely, the charge-transfer [13], the ultralow-power [9], and the high-speed [8] designs, respectively. In Section V, we describe a modified version of the proposed SA that can operate at a low supply voltage of 0.55 V. Section VI concludes the paper.…”

Section: Introductionmentioning

confidence: 99%

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Hybrid-Mode SRAM Sense Amplifiers: New Approach on Transistor Sizing

Kong

Yeo

2008

IEEE Trans. Circuits Syst. II

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A novel high-speed sense amplifier for ultra-lowvoltage SRAM applications is presented. It introduces a completely different way of sizing the aspect ratio of the transistors on the data-path, hence realizing a current-voltage hybrid mode Sense Amplifier. Extensive post-layout simulations have proved that the new Sense Amplifier provides both high-speed and low-power properties, with its delay and power reduced to 25.8% and 37.6% of those of the best prior art. It also offers a much better read-effectiveness and robustness against the bit-and data-line capacitances as well as V DD variations. Furthermore, the new Sense Amplifier is able to tolerate a large difference between the parasitic capacitances associated with the complementary DLs. It can operate down to a supply voltage of 0.9 V, the lowest reported for a 0.18 m CMOS process. A modified cross-coupled amplifier is also introduced, allowing the Sense Amplifier to operate down to 0.55 V.Index Terms-Low-power SRAM, low-voltage SRAM, sense amplifier (SA).

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Section: Performance Comparisionsmentioning

confidence: 97%

Section: A Current-mode Sa and Its Derivativesmentioning

confidence: 99%

Section: A Circuit Operationmentioning

confidence: 99%

Section: Performance Comparisionsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Hybrid-Mode SRAM Sense Amplifiers: New Approach on Transistor Sizing

Kong

Yeo

2008

IEEE Trans. Circuits Syst. II

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A full current-mode sense amplifier for low-power SRAM applications

Shern

Kong

et al. 2008

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems

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A full current-mode sense amplifier is presented. It extensively utilizes the cross-coupled inverters for both local and global sensing stages, hence achieving ultra low-power and ultra high-speed properties simultaneously. Its sensing delay and power consumption are almost independent of the bit-and dataline capacitances. Extensive pre-layout simulation results based on a 1.8 V/0.18 μm CMOS technology from Chartered Semiconductor Manufacturing Ltd. (CHRT) have verified that the new SA outperforms the best published designs with 64% and 45% speed and power consumption improvements respectively. Furthermore, the new design can operate down to a supply voltage of 1 V. These attributes of the proposed SA make it judiciously appropriate for the use in the contemporary highcomplexity systems, which continually crave for low-power and high-speed characteristics.

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