A shortest path adaptive routing technique for minimizing path collisions in hybrid optical network-on-chip

Lee, Jae Hoon; Kim, Young Seok; Li, Chang Lin; Han, Tae Hee

doi:10.1016/j.sysarc.2013.08.017

Cited by 5 publications

(4 citation statements)

References 24 publications

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“…Based on Lee [1], the best method to decrease path collisions is by using rollback scheme. Where the packet can rollback if the destination port is blocked.…”

Section: E Discussionmentioning

confidence: 99%

“…Lee [1] has introduced a technique called rollback scheme in his routing algorithm that can rolled back if the port has been blocked, this technique has improve the path collisions problem but introduced more power consumption. …”

Section: B Problem On Low Resources Utilizationmentioning

confidence: 99%

“…The third problem is energy consumption that happen due to inefficiency of routing algorithm that effects the energy usage in HONoC. Due to mechanism in [1], the rollback scheme has successfully reduce path collisions in circuit switching but as an effect has added extra energy usage in the HONoC.…”

Section: Introductionmentioning

confidence: 99%

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A review on path collisions and resources usage in hybrid optical Network on Chip (HONoC)

Razali

Othman

2015

2015 IEEE Student Conference on Research and Development (SCOReD)

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System-on-chip (SoC) architectures are getting communication-bound both from physical wiring and distributed computation point of view. Wiring delays are becoming dominating over gate delays, which favors short links. The larger SoC the more probably the overall computation is heterogeneous and localized rather than evenly balanced over the chip. These two factors motivate Network-on-Chip (NoC) that brings the techniques developed for macro-scale, multi-hop networks into a chip. But due to shrinkage of transistors and integration of billions of transistors in a single chip, has made NoC no longer suitable to cater for high latency and demand of bandwidth in a multicore processor environment. Thus they have introduce HONoC (hybrid optical network on chip) to cater for the high latency and demand in bandwidth. There are many research that focus on the area of architecture, routing algorithm and switching strategies in order to make the communication run optimally in HONoC. The purpose of this paper is to evaluate main problems in HONoC. From the evaluation, three main problems has been identified which are path collisions, low resource usage and high power consumption in HONoC

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“…Based on Lee [1], the best method to decrease path collisions is by using rollback scheme. Where the packet can rollback if the destination port is blocked.…”

Section: E Discussionmentioning

confidence: 99%

Section: B Problem On Low Resources Utilizationmentioning

confidence: 99%

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A review on path collisions and resources usage in hybrid optical Network on Chip (HONoC)

Razali

Othman

2015

2015 IEEE Student Conference on Research and Development (SCOReD)

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“…As the number of cores in the system increases, the network-size-scalable architecture is highly desirable. The widely-known mesh topology is chosen due to its simplicity and regularity in terms of layout, after considering the advantages of the topology revealed by existing studies on mesh-based HONoCs [4][5][6].…”

Section: Introductionmentioning

confidence: 99%

Power and Signal-to-Noise Ratio Optimization in Mesh-Based Hybrid Optical Network-on-Chip Using Semiconductor Optical Amplifiers

Jang

Kim

Li³

et al. 2019

Applied Sciences

Self Cite

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To address the performance bottleneck in metal-based interconnects, hybrid optical network-on-chip (HONoC) has emerged as a new alternative. However, as the size of the HONoC grows, insertion loss and crosstalk noise increase, leading to excessive laser source output power and performance degradation. Therefore, we propose a low-power scalable HONoC architecture by incorporating semiconductor optical amplifiers (SOAs). An SOA placement algorithm is developed considering insertion loss and crosstalk noise. Furthermore, we establish a worst-case crosstalk noise model of SOA-enabled HONoC and induce optimized SOA gains with respect to power consumption and performance, respectively. Extensive simulations for worst-case signal-to-noise ratio (SNR) and power consumption are conducted under various traffic patterns and different network sizes. Simulation results show that the proposed SOA-enabled HONoC architecture and the associated algorithm help sustain the performance as network size increases without additional laser source power.

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Optical Versus Electrical: Performance Evaluation of Network On-Chip Topologies for UWASN Manycore Processors

Yahya

Ali

et al. 2019

Wireless Pers Commun

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A shortest path adaptive routing technique for minimizing path collisions in hybrid optical network-on-chip

Cited by 5 publications

References 24 publications

A review on path collisions and resources usage in hybrid optical Network on Chip (HONoC)

A review on path collisions and resources usage in hybrid optical Network on Chip (HONoC)

Power and Signal-to-Noise Ratio Optimization in Mesh-Based Hybrid Optical Network-on-Chip Using Semiconductor Optical Amplifiers

Optical Versus Electrical: Performance Evaluation of Network On-Chip Topologies for UWASN Manycore Processors

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