A simple implementation of determinant decision diagram

Shi, Guoyong

doi:10.1109/iccad.2010.5654333

Cited by 7 publications

(3 citation statements)

References 9 publications

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“…The Hier-GPDD program implements the hierarchical GPDD method proposed in this paper, while the Hier-DDD program implements the hierarchical DDD method, which is also based on the symbolic stamp concept rather than the de-cancellation strategy implemented in [6], [11]. A recently proposed DDD algorithm [13] is implemented in the Hier-DDD program for DDD construction which is believed to be more efficient than the traditional implementation. All programs were implemented in C++ and executed on an Intel Core2 Duo T7100 1.80GHz processor with 2GB memory.…”

Section: Resultsmentioning

confidence: 99%

Hierarchical graph reduction approach to symbolic circuit analysis with data sharing and cancellation-free properties

Yang

Shi

2012

17th Asia and South Pacific Design Automation Conference

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Parallel to algebraic methods, graphical circuit analysis methods have the advantage of cancellation-free. This paper proposes a graph reduction method for hierarchical symbolic circuit analysis by applying a binary decision diagram (BDD) for data sharing. This method is extended from the Graph-Pair Decision Diagram (GPDD) method which was developed for two-port dependent sources. New graph construction rules for multiple-port dependent sources are introduced, with which large analog circuits can be analyzed hierarchically. The new hierarchical method guarantees the cancellation-free property at each layer of hierarchy. The BDD-based hierarchical analysis method can greatly reduce the analysis complexity of the entire circuit, while the software construction and circuit partition remain easy. The new method is compared to the algebraic hierarchical method based on DDD (Determinant Decision Diagram) which does not have the cancellation-free property. Comparable performance can be achieved with the new method which has the extra cancellation-free property.Index Terms-Analog integrated circuits, binary decision diagram (BDD), cancellation-free symbolic analysis, graph reduction, hierarchical analysis, multiple-port analysis.

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Section: Resultsmentioning

confidence: 99%

Hierarchical graph reduction approach to symbolic circuit analysis with data sharing and cancellation-free properties

Yang

Shi

2012

17th Asia and South Pacific Design Automation Conference

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“…For determinant expansion and transfer function formulation, DDD technique is used [22, 23]. Layer expansion digraph is used for reduction of DDD size.…”

Section: Symbolic Noise Modelling and Analysis Of A Differential Vcomentioning

confidence: 99%

Fast and optimised design of a differential VCO using symbolic technique and multi objective algorithms

Panda¹,

Patnaik

Mal

et al. 2019

IET Circuits, Devices & Systems

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In this work, a DVCO has been designed for a 4-bit, 10 MHz VCO based ADC. The noise modelling and analysis of this designed DVCO is carried out using layered determinant expansion based DDD technique. The results obtained using these methods are found to be nearly identical to that of SPICE. However, the computational time has been reduced from 13.7 sec using numerical method (SPICE) to 4.5 sec using DDD technique. Optimisation of the designed DVCO is then carried out using multi-objective optimisation techniques such as IDEA and MOPSO to enhance the performance. Low power and low phase noise at the desired frequency of oscillation were the optimisation goals. For this designed DVCO, IDEA optimisation approach seems to be more efficient than the MOPSO. The optimised DVCO is then simulated at different process corners using SPICE. The designed DVCO has shown improvement in phase noise from −80.3 dBc/Hz to −88.9 dBc/Hz at 1 MHz offset. The power consumption is also reduced from 38.4 mw to 34.5 mw and achieved a target frequency of 3.49 GHz. These improvements in the performance of the DVCO lead to an improvement in the ENOB from 3.6 to 4.2 bit of the designed ADC.

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“…The solution is then generated by applying the Cramer's rule [23]. One may also adopt a singular matrix formulation by filling the independent source in the left-hand side matrix [30].…”

Section: Compact Two-graph For Symbolic Analysismentioning

confidence: 99%

Two‐graph analysis of pathological equivalent networks

Shi

2014

Circuit Theory & Apps

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Recently, abstract current mirror and voltage mirror elements have been proposed for behavioral modeling of active analog blocks. Such artificial elements and the traditionally used nullor element together are called pathological elements in the literature. Pathological elements are very useful in modeling and analysis of active network. Hence, researchers have been motivated to study symbolic analysis methods for networks containing pathological elements. However, so far, only nodal admittance matrix analysis has been formulated. In this work, an alternative two-graph method is formulated, which has the advantage of providing a compact intermediate form for subsequent symbolic term generation. With a compact two-graph representation, either a matrix method or a tree enumeration method can be employed. For completeness, the classical two-graph theory has been extended in this paper to encompass all four types of dependent sources and all pathological elements. Illustrative examples are presented to demonstrate the principle of compact symbolic term generation by the presented two-graph method.The classical two-graph method developed in the 1960s was only applicable to networks containing RCL-g m elements, that is, elements of R (resistor), C (capacitor), L (inductor), and g m (voltage-controlled current 1128 G. SHI

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A simple implementation of determinant decision diagram

Cited by 7 publications

References 9 publications

Hierarchical graph reduction approach to symbolic circuit analysis with data sharing and cancellation-free properties

Hierarchical graph reduction approach to symbolic circuit analysis with data sharing and cancellation-free properties

Fast and optimised design of a differential VCO using symbolic technique and multi objective algorithms

Two‐graph analysis of pathological equivalent networks

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