A single-chip CMOS transceiver for 802.11a/b/g wireless LANs

Ahola, R.; Aktas, A.; Wilson, J.; Rao, Kishore Rama; Jönsson, Fredrik; Hyyrylainen, I.; Brolin, A.; Hakala, T.; Friman, A.; Makiniemi, T.; Hanze, J.; Sanden, M.; Wallner, D.; Guo, Yuxin; Lagerstam, T.; Noguer, L.; Knuuttila, Timo; Olofsson, P.; Ismail, Mohamed A.

doi:10.1109/jssc.2004.836334

Cited by 75 publications

(25 citation statements)

References 8 publications

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“…In principle, the phase tuning could be implemented in the signal path. But it would have to be linear and broadband [2]. As explained above, when implemented in the LO path, the phase tuning only needs to operate at a certain point frequency, and linearity requirement is also relaxed.…”

Section: Calibration Loop Designmentioning

confidence: 99%

“…The variable delay line is implemented in the last stage of the limiting buffer driving the mixer LO ports, modified from that of [2]. The last stage of the limiting buffer is composed of two source followers, as shown in Fig.…”

Section: Vdl Designmentioning

confidence: 99%

“…Owing to circuitry imperfection and limitation of local oscillator (LO) generation circuits, the actual quadrature accuracy is not so good as expected, resulting in reduced signal to noise ratio (SNR) and, hence, performance degradation [2]. In complex modulation schemes, such as 64-QAM, a quadrature phase accuracy better than 1 • and an amplitude accuracy better than 1% are required to guarantee that the quadrature inaccuracy is not limiting the overall performance [2].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Analysis and Design of an Auto-IQ Phase Calibration Circuit Based on DLL Using a Quadrature Phase Detector

Liu

Chen

2006

Analog Integr Circ Sig Process

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Section: Calibration Loop Designmentioning

confidence: 99%

Section: Vdl Designmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Analysis and Design of an Auto-IQ Phase Calibration Circuit Based on DLL Using a Quadrature Phase Detector

Liu

Chen

2006

Analog Integr Circ Sig Process

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“…The approach of [2] uses a resistor ladder to cancel amplitude error and also cancels phase error by changing gate-source capacitor.…”

Section: Introductionmentioning

confidence: 99%

A CMOS Quadrature LC Oscillator using Automatic Phase/Amplitude Calibration

Ghonoodi

Naimi

2011

Circuits Syst Signal Process

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In this paper, a novel LC quadrature oscillator (QO) is presented that can simply and automatically cancel the phase and amplitude errors raised by mismatches in LC tanks; the major source of phase and amplitude errors. The design is based on method of using unequal coupling factors in a parallel quadrature oscillator (P-QO). This method shows how we can cancel phase and amplitude errors simultaneously by choosing appropriate inversely proportional coupling factors. To cancel the errors, the proposed circuits first sense the phase error and increase or decrease the difference between the coupling factors accordingly. When tuning tail currents, the coupling factors can be simply adjusted. The entire system has a block diagram like a PLL. The dynamics of the proposed circuit is analyzed, and it is shown how the phase and amplitude error is canceled in response to an imposed LC tank mismatch. To evaluate the circuit, a QO has been designed to oscillate at 5 GHz with 1.8 V supply and 6.2 mA current consumption. The circuit has been simulated using TSMC 0.18 CMOS practical model where all the results confirm the analytical results.

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“…Further, as shown in Fig. 1(c), the first-and second-stage mixers are reused with an RF input switchable transconductance stage while the LO 1 signal is set approximately but not exactly halfway between the two operation bands [4]. Therefore, the first-downconverted signals are near and can be selected by choosing proper LO 2 , like a wideband IF architecture.…”

Section: Introductionmentioning

confidence: 99%

Sige HBT Dual-Conversion Weaver-Hartley Downconverters With High Image Rejection

Syu¹,

Meng²,

Yu³

et al. 2011

PIER C

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Abstract-2.4/5.7-GHz dual-band Weaver-Hartley dual-conversion downconverters are demonstrated using 0.35-µm SiGe heterojunction bipolar transistor (HBT) technology with/without a correlated local oscillator (LO) generator. In the first implementation, the correlated LO generator consists of a divide-by-two frequency divider, a frequency doubler and a single-sideband upconverter and thus LO 1 (= 2.5×LO 2 ) signal is generated. As a result, the downconverter with the correlated LO signals has image-rejection ratios of more than 39 dB for the first/second image signals (IRR 1 /IRR 2 ) of the dual-conversion system at both 2.4/5.7-GHz modes while the downconverter without the correlated LO generators has a 6-dB higher conversion gain and IRR 1 /IRR 2 of more than 44 dB with the same dc power consumption (excluding the LO generator). On the other hand, a 10-GHz WeaverHartley downconverter is demonstrated with a resonant LC load at the first-stage mixer to improve the conversion gain at high frequencies. The downconverter achieves a conversion gain of 8 dB with IRR 1 /IRR 2 better than 43/40 dB.

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A single-chip CMOS transceiver for 802.11a/b/g wireless LANs

Cited by 75 publications

References 8 publications

Analysis and Design of an Auto-IQ Phase Calibration Circuit Based on DLL Using a Quadrature Phase Detector

Analysis and Design of an Auto-IQ Phase Calibration Circuit Based on DLL Using a Quadrature Phase Detector

A CMOS Quadrature LC Oscillator using Automatic Phase/Amplitude Calibration

Sige HBT Dual-Conversion Weaver-Hartley Downconverters With High Image Rejection

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