A single-chip FM modem baseband CMOS LSI for land mobile telephone radio units

Habuka, Tatsuji; Murota, K.; Ishiwaka, M.; Kimura, T.

doi:10.1109/jssc.1985.1052355

Cited by 6 publications

(1 citation statement)

References 4 publications

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“…Assume that the initial phase error is +n or -n, then the phase error lies in the range -n/2 < BE < +n/2 and it provides correct decisions on the received data. The average acquisition time is one half of the maximum value determined by (4). Similar statements may apply when the DPLL begins to lose the synchronism due to noise or deep signal fading.…”

Section: B Majority Voting Circuitmentioning

confidence: 65%

A compact low-power VLSI transceiver for wireless communication

Bang

Choi

Sheu

et al. 1995

IEEE Trans. Circuits Syst. I

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A 3 V CMOS VLSI for dual-mode wireless communication systems has been designed and fabricated using the MOSIS scaleable CMOS technology. By using mixed analog and digital circuit design techniques, a single chip solution to baseband processing of data and supervisory audio tone signals in the analog transmission mode is possible. Key analog circuits include an anti-alias filter, two fifth-order low-pass filters, one sixth-order band-pass filter, an interpolator for sampling rate conversion, and two comparators. The digital modules perform data transmission and reception, error coding and decoding, as well as tone detection and regeneration. When implemented in the 2 pm CMOS technology from the MOSLS Service for low-cost low-power applications, the transceiver chip consumes less than 6 mW at receive-only mode. It is also quite suitable for batterypowered devices, such as portable terminals. Design technologies can be applied to future high-speed Wireless transceiver design. The architecture and circuits described in this chip can be used in aggressively scaled technologies even with the supply voltage reduced toward 1 V if the threshold voltage is proportionally decreased. I. INTRODUCTIO~OR ESTABLISHING high-capacity land mobile tele-F phone and data transmission systems, economical and high-performance mobile radio units have been developed and used in many cities over the world. New digital technologies have been employed to accommodate higher capacity by increasing the efficiency of frequency resources and the rapid trends in integrated data communication networks for computer and multimedia applications. In Europe, the panEuropean Groupe Special Mobile (GSM) [ 13 system has been established for voice and data communications. The dualmode, time-division multiple access (TDMA) [2]-[4] scheme has been adopted in the North America for the secondgeneration personal communication systems. By assigning multiple time slots in a single frequency channel, the channel capacity has increased manyfold and the compatibility with conventional analog system is maintained. Both systems employ complex speech compression and sophisticated digital modulation methods to accommodate high-quality voice and data communication with the minimal frequency bandwidth. In such systems, low-power and high-performance VLSI play an Manuscript important role in transmitting, receiving signals and correcting data errors occurred during the transmission via multi-path channels.A 3 V CMOS data transceiver chip for dual-mode wireless mobile communication systems is designed and fabricated using the mixed analog and digital CMOS design techniques. It provides a single chip solution to the processing of transmit and receive wideband data in both the analog mode and standby operation of the digital transmission mode. As an integrated data transceiver chip, it is especially designed to consume minimum power while achieving high performance operation at a 3 V supply voltage. To this end, circuit architectures and design are carefu'lly optimized. Low-po...

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Section: B Majority Voting Circuitmentioning

confidence: 65%

A compact low-power VLSI transceiver for wireless communication

Bang

Choi

Sheu

et al. 1995

IEEE Trans. Circuits Syst. I

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Multiphase pulse counting FM demodulator

Sawahashi

Yamao

Murota

1989

Electron. Comm. Jpn. Pt. I

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A new pulse counting FM demodulator which requires no extra outer part and is suitable for monolithic circuit integration is proposed. Although a pulse counting FM demodulator composed of digital logic circuits is suitable for monolithic circuit integration, it is difficult to realize high demodulation sensitivity with a quadrature demodulator or a Foster‐Seeley demodulator. Considering the application to narrowband FM mobile radio communication, a new FM demodulator based on multiphase pulse counting (MPC) scheme is proposed. The proposed demodulator has demodulation sensitivity nearly equal to that of existing demodulators, requires no adjustment, and has a low distortion rate. Its mechanism and circuit configuration are described. Basic characteristics, especially the demodulation sensitivity improvement, are then theoretically analyzed. Demodulation sensitivity and demodulation SINAD characteristics are experimentally validated; finally, single‐chip monolithic circuit integration of the MPC‐FM demodulator is prefabricated and its feasibility is shown.

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A multilevel data transmission baseband LSI using SC circuits

Nakayama

Ichihara

1990

Electron Comm Jpn Pt III

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The baseband circuit for multilevel data transmission system was implemented by LSI using SC circuit technology. The waveform‐shaping filter, the full‐wave rectifier for clock regeneration, the narrowband filter and other circuits were constructed by SC circuits. The size and the power dissipation were reduced by constructing all filters in time‐division multiplex. The chip area and the power dissipation in the SC circuit is proportional to the total capacitance, and the total capacitance is determined by the capacitance ratio and the unit capacitance. From such a viewpoint, the narrowband filter used in the clock regeneration is constructed by multirate, and the capacitance ratio was compressed using the N‐path filter. Capacitance partitioning is applied to high‐Q filters to suppress the capacitance ratio. Then by composing all capacitances as the integer multiples of the same unit capacitance, the desired ratio accuracy was achieved based on the unit capacitance of 0.1 pF. The problem of performance degradation due to integer capacitance ratio was minimized by the discrete approximation. When the N‐path filter is composed by the time‐division multiplex scheme, the performance may be degraded greatly due to the parasitic capacitance among wirings. This effect was analyzed and an improvement from the viewpoint of the layout was proposed. As a result, the multilevel data transmission baseband LSI was realized with the chip size of 4.3 × 4/2 mm2 and the power consumption of 35 mW.

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A single-chip FM modem baseband CMOS LSI for land mobile telephone radio units

Cited by 6 publications

References 4 publications

A compact low-power VLSI transceiver for wireless communication

A compact low-power VLSI transceiver for wireless communication

Multiphase pulse counting FM demodulator

A multilevel data transmission baseband LSI using SC circuits

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