A single chip speech periodicity detector

Cox, R.V.; Crochiere, R.

doi:10.1109/icassp.1982.1171638

Cited by 11 publications

(3 citation statements)

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“…Again we get the same surprising result that a buffer size of 2p,,, is sufficient for any rational expansion ratio. The above results show exactly what the requirements of the TDHS compression and expansion algorithms are 1) a pitch detector to supply p , 2) a multiplier to implement (1) and (6), and 3 ) a buffer size of 2p,,,. The pitch detector requirement can be separated from the TDHS algorithm by implementing it separately and then transmitting pitch to the TDHS algorithm in a multiplexed fashion with the input speech data.…”

Section: A Mathematical Description and Buffer Sizesmentioning

confidence: 57%

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Real-time implementation of time domain harmonic scaling of speech for rate modification and coding

Cox¹,

Crochiere²,

Johnston³

1983

IEEE Trans. Acoust., Speech, Signal Process.

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Time domain harmonic scaling (TDHS) has been realized in real time on the Bell Laboratories digital signal processing (DSP) integrated circuit. It is an algorithm that can expand or compress the bandwidth and sampling rate of speech by taking advantage of the pitch structure in the speech signal. As such it is useful in a variety of speech applications including speech coding, speech enhancement, and rate modification. A single DSP can perform compression and a second DSP can perform expansion. Both operations require pitch information to be supplied with the input speech. Included in the system is a real-time pitch/periodicity detector which has also been implemented on a single DSP. Its design is based on a novel modification of the autocorrelation function type pitch detector. This paper presents details of both the TDHS and pitch detector implementation and discusses their performances. In particular in this paper we discuss a 2: 1 compression and expansion system that has been used as part of a 9.6 kbit/s speech coder. TDHS was previously thought to require a much larger buffer than the RAM memory available in the DSP. We show that for all the compression/expansion ratios of interest the buffer size needed is twice the maximum pitch period.

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Section: A Mathematical Description and Buffer Sizesmentioning

confidence: 57%

“…As its name implies, TDHS is implemented in the time domain. It is based on pitch synchronous processing and requires pitch measurement for its implementation [6] . Thus, as part of the system we have also implemented a real-time pitch/periodicity detector on a DSP, based on a modified version of the autocorrelation algorithm [7].…”

Section: Introductionmentioning

confidence: 99%

Real-time implementation of time domain harmonic scaling of speech for rate modification and coding

Cox¹,

Crochiere²,

Johnston³

1983

IEEE Trans. Acoust., Speech, Signal Process.

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“…[Dubn76] και LSI [Cox82], περνάμε σε γενικού σκοπού DSPs, όπου ο αλγόριθμος ενσωματώνεται σε μία ολοκληρωμένη εφαρμογή, όπως ένα σύστημα Κωδικό-/ αποκωδικοποιητή Ομιλίας (Vocoder) [Holc86,Fett88]. Οι δυνατότητες για απαιτητικότερες σε πολυπλοκότητα εφαρμογές διευρύνονται με την εμφάνιση νεωτέρων DSPs, ακόμα και αν αυτοί είναι σταθερής υποδιαστολής [Texa87Se, Moto89].…”

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Αλγοριθμοι Για Συστηματα Κωδικοποιησης Ομιλιας Με Παραμετρους Σε Πλασματικο Χρονο

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A 9.6-kb/s DSP Speech Coder

Crochiere¹,

Cox²,

Johnston³

et al. 1982

Bell System Technical Journal

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A digital speech coder has been designed for real‐time operation at a data rate of 9.6 kb/s. The design is based on a combination of two speech compression techniques: Time‐Domain Harmonic Scaling (tdhs) and Sub‐Band Coding (sbc). It is a highly modularized hardware implementation using five Bell Laboratories Digital Signal Processor (dsp) integrated circuits as the key processing elements. Three dsps are used in the encoder for pitch detection, tdhs compression, and sub‐band encoding. Another two dsps are used in the receiver for sub‐band decoding and tdhs expansion. In this paper we describe the overall design of the system and discuss some of the techniques used to realize it in the dsp hardware in real time. General issues of the algorithm design, software implementation, and hardware design are considered.

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A single chip speech periodicity detector

Cited by 11 publications

References 10 publications

Real-time implementation of time domain harmonic scaling of speech for rate modification and coding

Real-time implementation of time domain harmonic scaling of speech for rate modification and coding

Αλγοριθμοι Για Συστηματα Κωδικοποιησης Ομιλιας Με Παραμετρους Σε Πλασματικο Χρονο

A 9.6-kb/s DSP Speech Coder

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