A Single-Inductor Dual-Ouput (SIDO) DC-DC Converter for Implantable Medical Devices in 180nm Standard CMOS Process

Liao, Po‐Yung; Chen, Yilun; Chen, Po-Hung

doi:10.1109/icecs.2018.8617929

Cited by 4 publications

(1 citation statement)

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“…Therefore, the power supply rejection ratio (PSRR) characteristic of the LDO is crucial to suppress the output voltage ripple of the SMPS. [15][16][17] Generally, increasing the PSRR bandwidth of an LDO requires an increase in current consumption, which prevents the realization of small-sized wearable devices capable of operating for extended periods. Studies to improve the PSRR are underway, and a typical example involves a circuit configuration using a feedforward capacitor (C ff ).…”

Section: Introductionmentioning

confidence: 99%

Low quiescent current LDO with FVF-based PSRR enhanced circuit for EEG recording wearable devices

Mii,

Kanemoto,

Hirose

2024

Jpn. J. Appl. Phys.

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This paper presents a low quiescent current low-dropout regulator (LDO) with an auxiliary amplifier, flipped voltage follower (FVF)-based power supply rejection ratio enhanced circuit (FBPEC) for electroencephalogram (EEG) recording devices. The FBPEC comprises a FVF filter, current mirror, and common-source amplifier. The FBPEC exploits the characteristics of FVF filter to reduce the current consumption and increase the gain at specific frequencies. The small-signal equivalent circuit reveals the dominant pole of the FBPEC, which is affected by the output impedance and load capacitance of the common-source amplifier. The proposed LDO is designed using a 0.18 μm CMOS process and has improved power supply rejection ratio (PSRR) up to 18 dB at frequencies above 10 kHz compared to the general LDO. The proposed LDO has a low no-load quiescent current 648 nA and a good figure-of-merit score compared to those of previous works, proving that the proposed circuit is an effective solution for use in wearable EEG recording devices.

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Section: Introductionmentioning

confidence: 99%