A Stable Low Power Dissipating 9 T SRAM for Implementation of 4 × 4 Memory Array with High Frequency Analysis

Abstract

Today's high speed data processing and memory storage operations demand immediate data write and retrieval to meet up to benchmark. To act as a volatile or nonvolatile data storage for electronic devices such as mobile phones, laptops the Static Random-Access Memory (SRAM) has been perfect choice for industrialists. So memory usage is significant and more than 65% of electronic devices uses memory as its heart. Nevertheless, memory turns out to be a leading factor affecting speed, power and data retention in a handheld system. The urge for optimization in power is all time relevant. The proposed system is designed to optimize a single bit memory cell of conventional static random access memory and hence developed a stable system with low power consumption and obtained significantly low Power-Delay-Product (PDP) by varying operating frequencies in MHz range. Also, a comparative analysis of a 4x4 SRAM array is carried out between 6T SRAM cell and 9T SRAM cell. Here62.83% power reduction is obtained in the proposed system as compared with the existing system at an operating frequency of 2GHz. In this paper, a power reduction of 62.273% is obtained for the array structure. The power dissipation and Power Delay Product [PDP] of the single bit 9T SRAM cell is also lower than the conventional 6T SRAM. Thus, the paper implements the proposed scheme of SRAM into an array along with all connecting peripherals.