A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier for an IR-WB receiver

Abstract

A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier (THA) in 0.13 m CMOS for an impulse radio ultra-wideband (IR-UWB) receiver is presented. The challenge is in implementing a sub-sampling ADC with ultra-high input signal that further exceeds the Nyquist frequency. This paper presents, to our knowledge for the second time, a sub-sampling ADC with input signals above 4 GHz operating at a sampling rate of 1.056 GHz. In this design, a novel THA is proposed to solve the degradation in amplitude and improve the linearity of signal with frequency increasing to giga Hz. A resistive averaging technique is carefully analyzed to relieve noise aliasing. A low-offset latch using a zero-static power dynamic offset cancellation technique is further optimized to realize the requirements of speed, power consumption and noise aliasing. The measurement results reveal that the spurious free dynamic range of the ADC is 30.1 dB even if the input signal is 4.2 GHz sampled at 1.056 GS/s. The core power of the ADC is 30 mW, excluding all of the buffers, and the active area is 0.6 mm 2 . The ADC achieves a figure of merit of 3.75 pJ/conversion-step.