A Subthreshold Surface Potential and Drain Current Model for Lateral Asymmetric Channel (LAC) MOSFETs

Abstract

A drift-diffusion theory based subthreshold drain current model for lateral asymmetric channel (LAC) MOSFET is presented. In this, an accurate analytical subthreshold surface potential model, in which the contribution of the varying depth of the channel depletion layer due to source and drain junctions have been accounted for is used. A physically-based empirical modification of the channel conduction layer thickness, originally proposed for relatively long-channel conventional devices, is also made for such short-channel asymmetrically doped devices. Very good agreement of both surface potential and drain current is observed between the model calculation and the prediction made by the 2-D numerical simulation using Dessis of ISE-TCAD. The performance prediction of the subthreshold analog circuits based on this model is also found to agree well with that by the numerical simulator.

Asymmetric halo and symmetric Single‐Halo Dual‐Material Gate and Double‐Halo Dual‐Material Gate n‐MOSFETs characteristic parameter modeling

“…The unknown voltages V 2 , V 3 , V 4 , V 5 , and V 6 are computed by applying the continuity of the electric field along the lateral direction (d Ψ s /d x ) at the interfaces of the various regions followed by the calculation of the surface potential Ψ s ( x ) as in Refs .…”

“…The corresponding depth of depletion layers are obtained as in the case of DHDMG MOSFET. The surface potential Ψ s ( x ) for all the five regions are determined as in Refs . The fitting parameters used in this case are the same as in the case of DHDMG MOSFET.…”

“…Dual-material gate structure uses two different metal gates with different work functions amalgameted together causing a step in surface potential profile. A dual-material gate MOSFET structure can provide improvement in reduction of SCE because the step shape in surface potential profile screens the effects of drain on the device channel, also resulting in an increase of the carrier transport efficiency by increasing the average electric field [1][2][3][11][12][13][14][15][16][17].…”

“…Over the years, various methods have been proposed for reducing the MOSFET dimension, keeping a constant electric field in the device . To reduce the short‐channel effects (SCEs), we used the channel engineering approach like single halo also known as lateral asymmetric channel or double‐halo implants.…”