A switched chaotic encryption scheme using multi-mode generalized modified transition map

Sayed, Wafaa S.; Tolba, Mohamed F.; Radwan, Ahmed G.; Abd-El-Hafiz, Salwa K.; Soliman, Ahmed M.

doi:10.1007/s11042-020-09756-y

Cited by 2 publications

(1 citation statement)

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“…The FPGA realization of IP core for generic fractionalorder derivative ,which allows the reconfigurability of fractional orders in the processing time, is required for different potential applications. This generic FPGA system can realize many fractional-order applications on hardware, e.g., edge detection [38], [39], control [40], [41], synchronization [42] and encryption [43]. Additionally, it can replace the current realizations of mixed-signal and digitally implemented fractional-order applications with the reconfigurable one, e.g., analog/mixed-signal systems [44], [45], control [46] and encryption [12], [47]- [49].…”

Section: Introductionmentioning

confidence: 99%

Reconfigurable FPGA Realization of Fractional-Order Chaotic Systems

et al. 2021

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This paper proposes FPGA realization of an IP core for generic fractional-order derivative based on Grünwald-Letnikov approximation. This generic design is applied to achieve reconfigurable realization of fractional-order chaotic systems. The fractional-order real-time configuration boosts the suitability of this particular realization for different applications, including dynamic switching, synchronization, and encryption. The proposed design targets optimized utilization of the FPGA internal resources and efficient employment of the external peripherals: switches and I/O ports in the FPGA board. The digital design of the fractional-order dependent terms: binomial coefficients and power function is proposed. Three approximations of the power function using curve fitting are compared, settling on the quadratic approximation that balances accuracy and efficiency. Three fractional-order chaotic systems: Liu, Li and Chen four-wing, are verified for both commensurate and incommensurate orders cases, using one approach for the commensurate order case and two approaches for the incommensurate order case. The reconfigurable design is realized on the Artix-7 FPGA board, yielding throughputs of 1.1266, 1.1266, and 1.434 Gbit/s for both commensurate and incommensurate orders cases of the three systems, respectively. Compared to recent related works, the proposed implementation demonstrates its efficient hardware utilization and suitability for potential applications.

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