A system for incremental synthesis to gate-level and reoptimization following RTL design changes

Abstract

W e address the problem of long cycle time associated with the basic method of optimizing VLSI circuits. W e are developing a system which makes it possible to carry out arbitrary changes to Register Transfer Level (RTL) source description of the circuit after a gatelevel implementation has been synthesized. The system incrementally updates the gate-level implementation. For typical changes this updation produces comparable results but requires only a small fraction of the time for a complete resynthesis. The system makes use of two object representations. W e describe these representations, the maintenance of consistency between them and the incremental synthesis and reoptimization process. Status of the ongoing research on this system is presented.