A system level processor/communication co-exploration methodology for multi-processor system-on-chip platforms

Software Performance Estimation in MPSoC Design

“…The integrated hardware and software simulation model we use is similar to that in the work proposed by (BENINI et al, 2005;WIEFERINK et al, 2004;BELANOVIC et al, 2004). These global simulation environments, usually called 'virtual prototypes', integrate an instruction-accurate or cycle-accurate simulator of the target processor with a hardware simulator.…”

“…FlexPerf enables extended analysis and the reuse of existing analysis modules. This work is similar to (WIEFERINK et al, 2004;BENINI et al, 2005), where a global synchronized MPSoC simulation model is presented. These environments provide certain performance analysis capabilities related to processor and communication performance.…”

“…Meyr et al (WIEFERINK et al, 2004) propose a link between simulation models generated with LISA and SystemC system-level simulation. The goal is to explore the processor and communication jointly, using a system-level approach.…”

An Integrated SystemC Debugging Environment

“…The GRACE++ system [16] uses SystemC simulation results to create Message Sequence Charts in order to visualize and analyze inter-process communication. Various filters help to reduce information complexity.…”

Evaluation of SystemC Modelling of Reconfigurable Embedded Systems

“…Previous related work include, amongst others, SystemC modelling of an IP forwarding chip [1], AMBA bus architecture [2], multiprocessor SoC platforms [3], and virtual in-circuit emulation [4]. This paper presents several different SystemC models of a complex embedded system executing uClinux operating system.…”