A System Verilog Approach for Verification of Memory Controller

Abstract

The major bottleneck of the computer system to improve the overall performance, is the memory performance. An effective control of data between processor and memory can be done using memory controller. Verification plays a vital role in any design flow as it is completed before silicon development. In this work a memory controller for interfacing Synchronous Static Random Access Memory (SSRAM), Synchronous Dynamic Random Access Memory (SDRAM), Read Only Memory (ROM) and FLASH which is Electrically ErasableProgrammable Read-Only Memory is designed and a Constraint random verification environment which is coverage driven, is built for the designed memory controller. The code is written in Verilog HDL and the verification is done using System Verilog. Using Questa Sim 10.0b software tool the simulation is done, and coverage results are obtained. The verification environment built in this work, gives a functional coverage of 96.8% and assertion success of 100% with 0% assertion failures. Simulation results show that the designed controller gave good performance and full filled all the system specifications.