A Systematic Methodology for Characterizing Scalability of DNN Accelerators using SCALE-Sim

Samajdar, Ananda; Joseph, Jan Moritz; Zhu, Yuhao; Whatmough, Paul N.; Mattina, Matthew; Krishna, Tushar

doi:10.1109/ispass48437.2020.00016

Cited by 136 publications

(66 citation statements)

References 17 publications

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“…They show that when we use larger systolic arrays (approaching the baseline size) the average PE array utilization always decreases. This behaviour has been documented in prior studies [20], [24] and occurs due to difficulties when mapping GEMM operations with irregular shapes. Input matrices fall into this category, when they have a dimension smaller than the width of the PE array.…”

Section: Resultssupporting

confidence: 64%

“…Instead of using a custom DNN framework, TFLITE-SOC integrates with Tensorflow Lite, which already has wide deployment and will be supported for the foreseeable future. SCALE-SIM is a Python-based cycle-accurate and configurable systolic array accelerator simulator proposed by Samajdar et al [24]. They use SCALE-SIM to provide analytical modeling to estimate the runtime of individual DNN operations on a systolic array.…”

Section: Related Workmentioning

confidence: 99%

“…Modeling and quantitatively evaluating the benefits of different DNN accelerator designs should be the first step before investing additional time and money on a production prototype. Recent work [23]- [26], discussed in detail in Section V, highlights how design space exploration and end-to-end evaluation of DNNs can be implemented at different levels of abstraction and integrated with custom made [24]- [26] or production [23] frameworks. These contributions effectively provide a path for fair comparison of accelerator enhancements.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Design Space Exploration of Accelerators and End-to-End DNN Evaluation with TFLITE-SOC

Agostini

Dong

Karimi

et al. 2020

2020 IEEE 32nd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)

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Section: Resultssupporting

confidence: 64%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Design Space Exploration of Accelerators and End-to-End DNN Evaluation with TFLITE-SOC

Agostini

Dong

Karimi

et al. 2020

2020 IEEE 32nd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)

View full text Add to dashboard Cite

“…Usually, the scale of GEMM in SConv layers is large and multiples of the array size. Tiling and processing these GEMMs (grey boxes) can fully utilize PEs (red boxes) in the SA [15], as shown in Fig. 2a.…”

Section: Introductionmentioning

confidence: 99%

Heterogeneous Systolic Array Architecture for Compact CNNs Hardware Accelerators

Xu¹,

Wang³

et al. 2021

IEEE Trans. Parallel Distrib. Syst.

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“…It should be noted that since MobileNet mostly runs on embedded or mobile terminals/devices, the array size would not be so large. At the same time, this scale-up method of the systolic array is not recommended because it will bring great performance loss [34].…”

Section: Resultsmentioning

confidence: 99%

Configurable Multi-directional Systolic Array Architecture for Convolutional Neural Networks

Wang

et al. 2021

ACM Trans. Archit. Code Optim.

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The systolic array architecture is one of the most popular choices for convolutional neural network hardware accelerators. The biggest advantage of the systolic array architecture is its simple and efficient design principle. Without complicated control and dataflow, hardware accelerators with the systolic array can calculate traditional convolution very efficiently. However, this advantage also brings new challenges to the systolic array. When computing special types of convolution, such as the small-scale convolution or depthwise convolution, the processing element (PE) utilization rate of the array decreases sharply. The main reason is that the simple architecture design limits the flexibility of the systolic array. In this article, we design a configurable multi-directional systolic array (CMSA) to address these issues. First, we added a data path to the systolic array. It allows users to split the systolic array through configuration to speed up the calculation of small-scale convolution. Second, we redesigned the PE unit so that the array has multiple data transmission modes and dataflow strategies. This allows users to switch the dataflow of the PE array to speed up the calculation of depthwise convolution. In addition, unlike other works, we only make a few changes and modifications to the existing systolic array architecture. It avoids additional hardware overheads and can be easily deployed in application scenarios that require small systolic arrays such as mobile terminals. Based on our evaluation, CMSA can increase the PE utilization rate by up to 1.6 times compared to the typical systolic array when running the last layers of ResNet-18. When running depthwise convolution in MobileNet, CMSA can increase the utilization rate by up to 14.8 times. At the same time, CMSA and the traditional systolic arrays are similar in area and energy consumption.

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A Systematic Methodology for Characterizing Scalability of DNN Accelerators using SCALE-Sim

Cited by 136 publications

References 17 publications

Design Space Exploration of Accelerators and End-to-End DNN Evaluation with TFLITE-SOC

Design Space Exploration of Accelerators and End-to-End DNN Evaluation with TFLITE-SOC

Heterogeneous Systolic Array Architecture for Compact CNNs Hardware Accelerators

Configurable Multi-directional Systolic Array Architecture for Convolutional Neural Networks

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