A Technology for Reducing Flicker Noise for ULSI Applications

Tanaka, Kiyofumi; Watanabe, Kazufumi; Ishino, Hideaki; Sugawa, Shigetoshi; Teramoto, Akinobu; Hirayama, Masaki; Ohmi, Tadahiro

doi:10.1143/jjap.42.2106

Cited by 25 publications

(16 citation statements)

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“…3,32 The alkali-free five-step cleaning process has been used to flatten the silicon-oxide interface. 12,33 The cleaning process has been repeated four times for the Si͑110͒ surfaces and only two times for the Si͑100͒ ones. This led to a very same microroughness for both surfaces.…”

Section: Methodsmentioning

confidence: 99%

“…In particular, it is essential to fabricate a gate insulator with a level of defect as low as possible 11 as well as an interface semiconductor/insulator as flat as possible. 12,13 As a consequence, the quality of processes involved in the fabrication of the gate insulator can be characterized by the evaluation of the low frequency noise. [14][15][16] Some are explaining the 1 / f noise through a bulk phenomenon induced by the fluctuation of mobility in the lattice, 17 first introduced during the 1970s by Hooge and generally noted ⌬, while others are attributing it to a fluctuation in the number of carriers caused by interface traps, 18,19 this model is the McWhorter one, generally abbreviated ⌬N.…”

Section: Introductionmentioning

confidence: 99%

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Different mechanism to explain the 1∕f noise in n- and p-SOI-MOS transistors fabricated on (110) and (100) silicon-oriented wafers

Gaubert

Teramoto

Cheng

et al. 2009

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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Articles you may be interested inAging mechanism of the native oxide on silicon (100) following atmospheric oxygen plasma cleaning J. Vac. Sci. Technol. A 29, 041403 (2011); 10.1116/1.3597436 Channel direction, effective field, and temperature dependencies of hole mobility in (110)-oriented Ge-oninsulator p-channel metal-oxide-semiconductor field-effect transistors fabricated by Ge condensation technique J. Appl. Phys. 109, 033709 (2011); 10.1063/1.3537919Influence of uniaxial mechanical stress on the high frequency performance of metal-oxide-semiconductor field effect transistors on (100) Si wafer Appl.

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Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Different mechanism to explain the 1∕f noise in n- and p-SOI-MOS transistors fabricated on (110) and (100) silicon-oriented wafers

Gaubert

Teramoto

Cheng

et al. 2009

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

Self Cite

View full text Add to dashboard Cite

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“…Therefore, high-k materials should be introduced instead of conventional SiO 2 gate insulator. Many institutions have reported so far the Si surface flattening process [17,18,19,20], and MOSFETs with atomically flat interface at Si/gate insulator show higher performances than those with conventional devices [21,22,23,24]. The 1/f noise in MOSFETs with Si/high-k gate stacks has also been reported [25,26].…”

Section: Introductionmentioning

confidence: 96%

Importance of Si surface flatness to realize high-performance Si devices utilizing ultrathin films with new material system

Ohmi

2014

IEICE Electron. Express

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The importance of Si surface flatness on metal-oxide-semiconductor field-effect transistor (MOSFET) characteristics with ultrathin hafnium oxynitride (HfON) high-k gate insulator formed by electron cyclotron resonance (ECR) plasma sputtering was described. The surface roughness of Si substrate was reduced by Ar/4.9%H 2 annealing utilizing conventional rapid thermal annealing (RTA) system. Si surface root-mean-square (RMS) roughness was well controlled by changing the annealing temperature from 700 to 1000°C. Si surface RMS roughness after 1000°C/1 hr annealing was 0.078 nm for Si(100) and 0.082 nm for Si(110), respectively. Clear dependence of electrical characteristics of MOS diodes such as equivalent oxide thickness (EOT) and leakage current on the surface RMS roughness of Si(100) and Si(110) was observed, and the electrical characteristics were remarkably improved by decreasing of surface RMS roughness. The MOSFET characteristics with HfON gate insulator fabricated on Si(100) substrates after flattening process were also improved.

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“…This improvement is related to the strongly improved surface roughness/uniformity and defect density. It was in fact demonstrated that the formation of the atomic scale flattened Si/SiO 2 interface by a radical oxidation technique is effective in reducing the 1/f noise at least in n-channel MOSFETs [66]. …”

Section: Impact Of Pocket Implantsmentioning

confidence: 99%

1/f noise in deep-submicron CMOS technology for RF and analog applications

et al. 2004

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As further enhanced functionalities of mobile equipment are predicted, the development of a CMOS technology that provides low-power, high-speed, and low-noise performance has become an urgent and hot issue. For these application driven technologies the complexity must be tackled at different levels to insure the optimisation of the area, the power consumption, the speed and the reliability. Therefore this paper present a review of the solutions implemented at different levels from system down to technology in order to reduce the contribution of the low frequency noise. These achievements are illustrated by experimental results from literature and are inserted in the general context of system design strategies for reducing the 1/f noise contribution. In a first part dedicated to high-level system and circuit design, we introduce the noise reduction by switching techniques and the methodology for including the noise dispersion in scaled devices for the early design of analogue/RF circuits. In the second part, the 1/f noise is tackled at its origins i.e. the choice of the gate oxide and other critical process steps.

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A Technology for Reducing Flicker Noise for ULSI Applications

Cited by 25 publications

References 0 publications

Different mechanism to explain the 1∕f noise in n- and p-SOI-MOS transistors fabricated on (110) and (100) silicon-oriented wafers

Different mechanism to explain the 1∕f noise in n- and p-SOI-MOS transistors fabricated on (110) and (100) silicon-oriented wafers

Importance of Si surface flatness to realize high-performance Si devices utilizing ultrathin films with new material system

1/f noise in deep-submicron CMOS technology for RF and analog applications

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