A total cost approach to evaluating different reconfigurable architectures for baseband processing in wireless receivers

Baines, R.; Pulley, Doug

doi:10.1109/mcom.2003.1166666

Cited by 36 publications

(18 citation statements)

References 3 publications

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“…The mean number or error free bits is 11, 14 and 16, for n iter = 5, 8 and 10 respectively. Hence, the proposed architecture is particularly suitable for scenarios where consecutive fast complex divisions are required, and a certain average error level is tolerated [14][15][16]21].…”

Section: Resultsmentioning

confidence: 99%

“…Otherwise, the possibility of real-time reconfiguration of hardware components is of utmost importance in current DSP systems [14]. A good example is found on channel estimation in adaptive digital modulation, either for single antenna [15] or multiantenna configurations [16], where the required accuracy (and therefore latency) on the inversion of the channel frequency response may vary according to the selected modulation scheme and the target bit error rate (BER).…”

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confidence: 99%

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Iterative-Gradient Based Complex Divider FPGA Core with Dynamic Configurability of Accuracy and Throughput

López‐Martínez

Castillo-Sánchez

Entrambasaguas

et al. 2010

J Sign Process Syst

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A field programmable gate array (FPGA) implementation of a highly configurable complex divider is presented, based on an iterative gradient algorithm. The proposed architecture allows to configure both the accuracy and the throughput of the division operation, which makes it suitable for diverse applications with different requirements. Results show how various throughputs can be achieved under different maximum error and iteration limit configurations. Besides, the resource occupation is considerably small, compared with previous solutions.

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Section: Resultsmentioning

confidence: 99%

mentioning

confidence: 99%

Iterative-Gradient Based Complex Divider FPGA Core with Dynamic Configurability of Accuracy and Throughput

López‐Martínez

Castillo-Sánchez

Entrambasaguas

et al. 2010

J Sign Process Syst

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show abstract

“…Among the various DSP algorithms, FIR filters are one of the most important algorithms which are widely used in numerous applications. Due to the high amount of MAC operations inherent in an FIR filter, state-of-the-art FPGAs are often used to implement FIR filters [58,86,[162][163][164][165][166][167][168][169].…”

Section: Fpgas For Dsp Implementationmentioning

confidence: 99%

“…It allows for a high throughput even at low MHz clock rates. This has given birth to a new type of processing called reconfigurable processing, where FPGAs perform time intensive tasks instead of software [161,166,189,190].…”

Section: E Reconfigurable Dsp Implementation On Fpgamentioning

confidence: 99%

Techniques for Efficient Implementation of FIR and Particle Filtering

Alam

2016

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Finite-length impulse response (FIR) filters occupy a central place many signal processing applications which either alter the shape, frequency or the sampling frequency of the signal. FIR filters are used because of their stability and possibility to have linear-phase but require a high filter order to achieve the same magnitude specifications as compared to infinite impulse response (IIR) filters. Depending on the size of the required transition bandwidth the filter order can range from tens to hundreds to even thousands. Since the implementation of the filters in digital domain requires multipliers and adders, high filter orders translate to a large number of these arithmetic units for its implementation. Research towards reducing the complexity of FIR filters has been going on for decades and the techniques used can be roughly divided into two categories; reduction in the number of multipliers and simplification of the multiplier implementation.One technique to reduce the number of multipliers is to use cascaded subfilters with lower complexity to achieve the desired specification, known as frequency-response masking (FRM). One of the sub-filters is a upsampled model filter whose band edges are an integer multiple, termed as the period L, of the target filter's band edges. Other sub-filters may include complement and masking filters which filter different parts of the spectrum to achieve the desired response. From an implementation point-of-view, time-multiplexing is beneficial because generally the allowable maximum clock frequency supported by the current state-of-the-art semiconductor technology does not correspond to the application bound sample rate. A combination of these two techniques plays a significant role towards efficient implementation of FIR filters. Part of the work presented in this dissertation is architectures for time-multiplexed FRM filters that benefit from the inherent sparsity of the periodic model filters.These time-multiplexed FRM filters not only reduce the number of multipliers but lowers the memory usage. Although the FRM technique requires a higher number delay elements, it results in fewer memories and more energy efficient memory schemes when time-multiplexed. Different memory arrangements and memory access schemes have also been discussed and compared in terms of their efficiency when using both single and dual-port memories. An efficient v vi Abstract pipelining scheme has been proposed which reduces the number of pipelining registers while achieving similar clock frequencies. The single optimal point where the number of multiplications is minimum for non-time-multiplexed FRM filters is shown to become a function of both the period, L and time-multiplexing factor, M . This means that the minimum number of multipliers does not always correspond to the minimum number of multiplications which also increases the flexibility of implementation. These filters are shown to achieve power reduction between 23% and 68% for the considered examples.To simplify the multiplier, alt...

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“…Typical implementations of software-defined radio (SDR) systems include a generalpurpose processor (GPP), a digital signal processor (DSP), or an FPGA, though dedicated DSP chips are being challenged by FPGAs with embedded DSP cores [27]. FPGA-based systems can deliver the performance but at the cost of increased design complexity.…”

Section: Diverse Range Of Processorsmentioning

confidence: 99%

Software-Defined Radio Demonstrators: An Example and Future Trends

Farrell

Sánchez

Corley

2009

International Journal of Digital Multimedia Broadcasting

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Software-defined radio requires the combination of software-based signal processing and the enabling hardware components. In this paper, we present an overview of the criteria for such platforms and the current state of development and future trends in this area. This paper will also provide details of a high-performance flexible radio platform called the maynooth adaptable radio system (MARS) that was developed to explore the use of software-defined radio concepts in the provision of infrastructure elements in a telecommunications application, such as mobile phone basestations or multimedia broadcasters.

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A total cost approach to evaluating different reconfigurable architectures for baseband processing in wireless receivers

Cited by 36 publications

References 3 publications

Iterative-Gradient Based Complex Divider FPGA Core with Dynamic Configurability of Accuracy and Throughput

Iterative-Gradient Based Complex Divider FPGA Core with Dynamic Configurability of Accuracy and Throughput

Techniques for Efficient Implementation of FIR and Particle Filtering

Software-Defined Radio Demonstrators: An Example and Future Trends

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