A Two-Stage Switched-Capacitor Integrator for High Gain Inverter-Like Architectures

Abstract

A discrete-time, switched capacitor integrator is presented. The integrator is based on a two-stage architecture where the first stage converts the input voltage into a charge that is accumulated into the second stage. The main strength of the proposed circuit is a higher dc gain with respect to previous solutions, making it optimal for low-voltage inverter-like integrators. A further advantage is the fact that, in contrast with existing solutions, the output voltage is valid across the whole clock cycle. Theoretical analysis of the circuit is performed to calculate the dependence of the integrator dc gain and input-referred offset voltage on the corresponding parameters of the constituting amplifiers. Discrete-time simulations are performed to estimate the gain and phase error with respect to an ideal integrator. The results of electrical simulations performed on an inverter-like prototype, designed with the UMC 0.18 m CMOS process, are presented to show the impact of non-idealities from the amplifiers and switches.

Ultra-Low-Voltage Inverter-Based Amplifier with Novel Common-Mode Stabilization Loop

“…This is possible because, despite the absence of a non-inverting input, in most SC circuits the operational amplifier non-inverting terminal is grounded, or, equivalently, fixed to a constant voltage to meet input common-mode (CM) range requirements. The relatively small dc gain of inverter-like amplifiers can be overcome by using SC architectures capable of boosting the overall dc gain to the square [5] or even the cube (using two inverter stages) [6] of the original inverter gain. Considering this fact, as already stated, the ideal application of this kind of amplifiers lies just in SC circuits, such as discrete-time integrators, which are the main building blocks of state-variable filters and ΔΣ modulators [7].…”

A Low-Power CMOS Bandgap Voltage Reference for Supply Voltages Down to 0.5 V

“…The amplifier OP was replaced by a Discrete Time (DT) Switched Capacitor (SC) integrator (DTI), enclosed inside the blue dotted polygon in Figure 6. The integrator was presented for the first time in [34] and was selected for the proposed LV-VR since it offers the following unique combination of properties: (i) it operates CDS, reducing the input-referred offset voltage and low frequency noise; (ii) its output voltage is valid across the whole clock cycle, making it equivalent to a continuous-time integrator; (iii) it ideally does not draw current from the inputs as soon as the virtual short-circuit is established; (iv) it provides a high DC gain. The integrator is formed by two stages, built around amplifiers A 1 and A 2 .…”

“…Switches are labeled with numbers that indicate the clock phase where they are closed (on state). The detailed operating principle of the SC integrator was analyzed in [34]. Briefly, in the transition between Phase 2 to Phase 1, a charge proportional to the input differential voltage (…”

“…In order to give experimental support to the proposed core topology, we designed a prototype using a 0.18 µm CMOS process. The feedback connection required by this class of VRs is provided in the prototype by a recently introduced switched capacitor integrator, having an always-available output voltage and intrinsic offset and flicker noise cancellation [34]. This integrator was already used in the combination of a BJT bandgap core in a differential-output VR designed for the 1.4-3.3 V V dd range [35].…”

“…This integrator was already used in the combination of a BJT bandgap core in a differential-output VR designed for the 1.4-3.3 V V dd range [35]. In this work, we used an inverter-like version of the integrator, capable of working with V dd down to 0.5 V [34]. It was already used in combination with an equivalent Kujik-like switched-capacitor core with a diode-connected MOSFET [36].…”