A Unified 4/8/16/32-Point Integer IDCT Architecture for Multiple Video Coding Standards

Shen, S. C.; Sui, Weiwei; Fan, Yibo; Zeng, Xiaoyang

doi:10.1109/icme.2012.7

Cited by 69 publications

(53 citation statements)

References 6 publications

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“…Park은 16x16 그리고 32x32 역변환 구조를 제시했다 [4] . Shen은 4/8/16/32-포인트 정수형 IDCT를 지원하는 곱셈 기 기반의 구조를 제안했다 [5] . 그리고 2013년에 Zhu는 파 이프라인 역변환 구조를 제안했다 [6] .…”

Section: 일정한 영상을 제공한다unclassified

Integer Inverse Transform Structure Based on Matrix for VP9 Decoder

Lee¹,

Hwang²,

Kim³

et al. 2016

Journal of the Institute of Electronics and Information Enginee

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In this paper, we propose an efficient integer inverse transform structure for vp9 decoder. The proposed structure is a hardware structure which is easy to control and requires less hardware resources, and shares algorithms for realizing entire DCT(Discrete Cosine Transform), ADST(Asymmetric Discrete Sine Transform) and WHT(Walsh-Hadamard Transform) in vp9. The integer inverse transform for vp9 google model has a fast structure, named butterfly structure. The integer inverse transform for google C model, unlike universal fast structure, takes a constant rounding shift operator on each stage and includes an asymmetrical sine transform structure. Thus, the proposed structure approximates matrix coefficient values for all transform mode and is used to matrix operation method. With the proposed structure, shared operations for all inverse transform algorithm modes can be possible with reduced number of multipliers compared to the butterfly structure, which in turn manages the hardware resources more efficiently.

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Section: 일정한 영상을 제공한다unclassified

Integer Inverse Transform Structure Based on Matrix for VP9 Decoder

Lee¹,

Hwang²,

Kim³

et al. 2016

Journal of the Institute of Electronics and Information Enginee

View full text Add to dashboard Cite

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“…According to the input throughput of these architectures, the work frequency with 4096×2048@30 fps realtime application is as low as 4.19 MHz. Compared with [8], our architecture can save about 45% hardware overhead and only need 1/8 transpose memory peak bandwidth. Compared with [7], our architecture only need 25% input access bandwidth to deal with all kinds of block size and block mode of IDCT/IDST with higher hardware utilization rate while only increasing 15.7% hardware cost.…”

Section: 3mentioning

confidence: 99%

“…According to the paper, its hardware utilization rate maybe less than 80%. Since the reference [8]'s architecture is based on 32-point IDCT butterfly computation structure, most blocks of it will be idle during the variable block size IDCT process. According to previous statistical results, the percentage of 16×16 block size used for IDCT is 9.1%, 32×32 block size used for IDCT almost 1.3%.…”

Section: 3mentioning

confidence: 99%

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A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard

Hong

Zhu

et al. 2013

IEICE Electron. Express

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High Efficiency Video Coding (HEVC) is the currently developing video coding standard beyond H.264/AVC. In this paper, a full pipelined 2-D IDCT/IDST VLSI architecture compatible with HEVC standard is presented for the first time. The proposed architecture supports adaptive block size IDCT from 4×4 to 32×32 pixels as well as IDST while keeping nearly 100% hardware utilization. Using SMIC 65 nm 1P9M technology, the synthesis results show that the architecture achieves the maximum work frequency at 480 MHz and the hardware cost is about 115.8 K Gates. Experimental results show that the proposed architecture is able to deal with realtime HEVC IDCT/IDST of 4 K×2 K (4096×2048)@30 fps video sequence at 171 MHz in average. In consequence, it offers a costeffective solution for the future UHDTV applications.

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“…Based on the traditional butterfly computational structure, S. Shen [3] et al presented a unified 4/8/16/32-point integer IDCT architecture in 2012 and W. Zhao [4] et al proposed a multiplierless inverse transform architecture in 2013, for HEVC 4K Â 2K video applications. To support different block size IDCT dynamically, P. T. Chiang [5] et al proposed a reconfigurable inverse transform architecture for HEVC 4K Â 2K video decoding in 2013.…”

Section: Introductionmentioning

confidence: 99%

Area-efficient HEVC IDCT/IDST architecture for 8K × 4K video decoding

Hong

et al. 2016

IEICE Electron. Express

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High Efficiency Video Coding (HEVC) is the newest video coding standard beyond H.264/AVC. To more efficiently compress image frames, variable block size DCT/IDCT (from 4 × 4 to 32 × 32) as well as 4 × 4 DST/IDST is employed by HEVC. In this paper, a novel area-efficient IDCT/IDST architecture for Ultra-High Definition (UHD) video applications is proposed. To reduce hardware cost and improve throughput efficiency, a novel resource sharing scheme, a template-based constant multiplication structure and a transpose buffer structure are adopted. Experimental results show that the proposed architecture can address 8K × 4K (7680 × 4320, 30 fps) video sequences at 390 MHz with at least a 39.5% gate count savings. Consequently, the proposed architecture offers a cost-efficient solution for future UHD applications.

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A Unified 4/8/16/32-Point Integer IDCT Architecture for Multiple Video Coding Standards

Cited by 69 publications

References 6 publications

Integer Inverse Transform Structure Based on Matrix for VP9 Decoder

Integer Inverse Transform Structure Based on Matrix for VP9 Decoder

A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard

Area-efficient HEVC IDCT/IDST architecture for 8K × 4K video decoding

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